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793 lines
51 KiB
C
793 lines
51 KiB
C
/******************************************************************************
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* Filename: hw_pka.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_PKA_H__
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#define __HW_PKA_H__
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//*****************************************************************************
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//
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// The following are defines for the PKA register offsets.
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//
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//*****************************************************************************
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#define PKA_APTR 0x44004000 // PKA vector A address During
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// execution of basic PKCP
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// operations, this register is
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// double buffered and can be
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// written with a new value for the
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// next operation; when not
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// written, the value remains
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// intact. During the execution of
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// sequencer-controlled complex
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// operations, this register may
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// not be written and its value is
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// undefined at the conclusion of
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// the operation. The driver
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// software cannot rely on the
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// written value to remain intact.
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#define PKA_BPTR 0x44004004 // PKA vector B address During
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// execution of basic PKCP
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// operations, this register is
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// double buffered and can be
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// written with a new value for the
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// next operation; when not
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// written, the value remains
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// intact. During the execution of
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// sequencer-controlled complex
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// operations, this register may
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// not be written and its value is
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// undefined at the conclusion of
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// the operation. The driver
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// software cannot rely on the
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// written value to remain intact.
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#define PKA_CPTR 0x44004008 // PKA vector C address During
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// execution of basic PKCP
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// operations, this register is
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// double buffered and can be
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// written with a new value for the
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// next operation; when not
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// written, the value remains
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// intact. During the execution of
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// sequencer-controlled complex
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// operations, this register may
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// not be written and its value is
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// undefined at the conclusion of
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// the operation. The driver
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// software cannot rely on the
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// written value to remain intact.
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#define PKA_DPTR 0x4400400C // PKA vector D address During
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// execution of basic PKCP
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// operations, this register is
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// double buffered and can be
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// written with a new value for the
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// next operation; when not
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// written, the value remains
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// intact. During the execution of
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// sequencer-controlled complex
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// operations, this register may
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// not be written and its value is
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// undefined at the conclusion of
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// the operation. The driver
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// software cannot rely on the
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// written value to remain intact.
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#define PKA_ALENGTH 0x44004010 // PKA vector A length During
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// execution of basic PKCP
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// operations, this register is
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// double buffered and can be
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// written with a new value for the
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// next operation; when not
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// written, the value remains
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// intact. During the execution of
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// sequencer-controlled complex
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// operations, this register may
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// not be written and its value is
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// undefined at the conclusion of
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// the operation. The driver
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// software cannot rely on the
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// written value to remain intact.
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#define PKA_BLENGTH 0x44004014 // PKA vector B length During
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// execution of basic PKCP
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// operations, this register is
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// double buffered and can be
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// written with a new value for the
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// next operation; when not
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// written, the value remains
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// intact. During the execution of
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// sequencer-controlled complex
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// operations, this register may
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// not be written and its value is
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// undefined at the conclusion of
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// the operation. The driver
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// software cannot rely on the
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// written value to remain intact.
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#define PKA_SHIFT 0x44004018 // PKA bit shift value For basic
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// PKCP operations, modifying the
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// contents of this register is
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// made impossible while the
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// operation is being performed.
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// For the ExpMod-variable and
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// ExpMod-CRT operations, this
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// register is used to indicate the
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// number of odd powers to use
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// (directly as a value in the
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// range 1-16). For the ModInv and
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// ECC operations, this register is
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// used to hold a completion code.
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#define PKA_FUNCTION 0x4400401C // PKA function This register
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// contains the control bits to
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// start basic PKCP as well as
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// complex sequencer operations.
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// The run bit can be used to poll
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// for the completion of the
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// operation. Modifying bits [11:0]
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// is made impossible during the
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// execution of a basic PKCP
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// operation. During the execution
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// of sequencer-controlled complex
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// operations, this register is
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// modified; the run and stall
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// result bits are set to zero at
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// the conclusion, but other bits
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// are undefined. Attention:
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// Continuously reading this
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// register to poll the run bit is
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// not allowed when executing
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// complex sequencer operations
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// (the sequencer cannot access the
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// PKCP when this is done). Leave
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// at least one sysclk cycle
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// between poll operations.
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#define PKA_COMPARE 0x44004020 // PKA compare result This
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// register provides the result of
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// a basic PKCP compare operation.
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// It is updated when the run bit
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// in the PKA_FUNCTION register is
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// reset at the end of that
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// operation. Status after a
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// complex sequencer operation is
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// unknown
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#define PKA_MSW 0x44004024 // PKA most-significant-word of
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// result vector This register
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// indicates the (word) address in
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// the PKA RAM where the most
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// significant nonzero 32-bit word
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// of the result is stored. Should
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// be ignored for modulo
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// operations. For basic PKCP
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// operations, this register is
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// updated when the run bit in the
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// PKA_FUNCTION register is reset
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// at the end of the operation. For
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// the complex-sequencer controlled
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// operations, updating of the
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// final value matching the actual
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// result is done near the end of
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// the operation; note that the
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// result is only meaningful if no
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// errors were detected and that
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// for ECC operations, the PKA_MSW
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// register will provide
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// information for the x-coordinate
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// of the result point only.
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#define PKA_DIVMSW 0x44004028 // PKA most-significant-word of
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// divide remainder This register
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// indicates the (32-bit word)
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// address in the PKA RAM where the
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// most significant nonzero 32-bit
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// word of the remainder result for
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// the basic divide and modulo
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// operations is stored. Bits [4:0]
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// are loaded with the bit number
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// of the most-significant nonzero
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// bit in the most-significant
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// nonzero word when MS one control
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// bit is set. For divide, modulo,
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// and MS one reporting, this
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// register is updated when the RUN
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// bit in the PKA_FUNCTION register
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// is reset at the end of the
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// operation. For the complex
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// sequencer controlled operations,
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// updating of bits [4:0] of this
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// register with the
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// most-significant bit location of
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// the actual result is done near
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// the end of the operation. The
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// result is meaningful only if no
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// errors were detected and that
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// for ECC operations; the
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// PKA_DIVMSW register provides
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// information for the x-coordinate
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// of the result point only.
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#define PKA_SEQ_CTRL 0x440040C8 // PKA sequencer control and
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// status register The sequencer is
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// interfaced with the outside
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// world through a single control
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// and status register. With the
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// exception of bit [31], the
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// actual use of bits in the
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// separate sub-fields of this
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// register is determined by the
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// sequencer firmware. This
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// register need only be accessed
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// when the sequencer program is
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// stored in RAM. The reset value
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// of the RESTE bit depends upon
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// the option chosen for sequencer
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// program storage.
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#define PKA_OPTIONS 0x440040F4 // PKA hardware options register
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// This register provides the host
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// with a means to determine the
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// hardware configuration
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// implemented in this PKA engine,
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// focused on options that have an
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// effect on software interacting
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// with the module. Note: (32 x
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// (1st LNME nr. of PEs + 1st LNME
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// FIFO RAM depth - 10)) equals the
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// maximum modulus vector length
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// (in bits) that can be handled by
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// the modular exponentiation and
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// ECC operations executed on a PKA
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// engine that includes an LNME.
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#define PKA_SW_REV 0x440040F8 // PKA firmware revision and
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// capabilities register This
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// register allows the host access
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// to the internal firmware
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// revision number of the PKA
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// Engine for software driver
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// matching and diagnostic
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// purposes. This register also
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// contains a field that encodes
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// the capabilities of the embedded
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// firmware. The PKA_SW_REV
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// register is written by the
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// firmware within a few clock
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// cycles after starting up that
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// firmware. The hardware reset
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// value is zero, indicating that
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// the information has not been
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// written yet.
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#define PKA_REVISION 0x440040FC // PKA hardware revision register
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// This register allows the host
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// access to the hardware revision
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// number of the PKA engine for
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// software driver matching and
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// diagnostic purposes. It is
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// always located at the highest
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// address in the access space of
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// the module and contains an
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// encoding of the EIP number (with
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// its complement as signature) for
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// recognition of the hardware
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// module.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_APTR register.
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//
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//*****************************************************************************
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#define PKA_APTR_APTR_M 0x000007FF // This register specifies the
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// location of vector A within the
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// PKA RAM. Vectors are identified
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// through the location of their
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// least-significant 32-bit word.
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// Note that bit [0] must be zero
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// to ensure that the vector starts
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// at an 8-byte boundary.
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#define PKA_APTR_APTR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_BPTR register.
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//
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//*****************************************************************************
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#define PKA_BPTR_BPTR_M 0x000007FF // This register specifies the
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// location of vector B within the
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// PKA RAM. Vectors are identified
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// through the location of their
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// least-significant 32-bit word.
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// Note that bit [0] must be zero
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// to ensure that the vector starts
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// at an 8-byte boundary.
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#define PKA_BPTR_BPTR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_CPTR register.
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//
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//*****************************************************************************
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#define PKA_CPTR_CPTR_M 0x000007FF // This register specifies the
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// location of vector C within the
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// PKA RAM. Vectors are identified
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// through the location of their
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// least-significant 32-bit word.
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// Note that bit [0] must be zero
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// to ensure that the vector starts
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// at an 8-byte boundary.
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#define PKA_CPTR_CPTR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_DPTR register.
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//
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//*****************************************************************************
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#define PKA_DPTR_DPTR_M 0x000007FF // This register specifies the
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// location of vector D within the
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// PKA RAM. Vectors are identified
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// through the location of their
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// least-significant 32-bit word.
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// Note that bit [0] must be zero
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// to ensure that the vector starts
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// at an 8-byte boundary.
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#define PKA_DPTR_DPTR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_ALENGTH register.
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//
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//*****************************************************************************
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#define PKA_ALENGTH_ALENGTH_M 0x000001FF // This register specifies the
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// length (in 32-bit words) of
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// Vector A.
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#define PKA_ALENGTH_ALENGTH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_BLENGTH register.
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//
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//*****************************************************************************
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#define PKA_BLENGTH_BLENGTH_M 0x000001FF // This register specifies the
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// length (in 32-bit words) of
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// Vector B.
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#define PKA_BLENGTH_BLENGTH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_SHIFT register.
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//
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//*****************************************************************************
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#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M \
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0x0000001F // This register specifies the
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// number of bits to shift the
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// input vector (in the range 0-31)
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// during a Rshift or Lshift
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// operation.
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#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PKA_FUNCTION register.
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//
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//*****************************************************************************
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#define PKA_FUNCTION_STALL_RESULT \
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0x01000000 // When written with a 1b,
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// updating of the PKA_COMPARE,
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// PKA_MSW and PKA_DIVMSW
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// registers, as well as resetting
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// the run bit is stalled beyond
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// the point that a running
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// operation is actually finished.
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// Use this to allow software
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// enough time to read results from
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// a previous operation when the
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// newly started operation is known
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// to take only a short amount of
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// time. If a result is waiting,
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// the result registers is updated
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// and the run bit is reset in the
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// clock cycle following writing
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// the stall result bit back to 0b.
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// The Stall result function may
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// only be used for basic PKCP
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// operations.
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#define PKA_FUNCTION_STALL_RESULT_M \
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0x01000000
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#define PKA_FUNCTION_STALL_RESULT_S 24
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#define PKA_FUNCTION_RUN 0x00008000 // The host sets this bit to
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// instruct the PKA module to begin
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// processing the basic PKCP or
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// complex sequencer operation.
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// This bit is reset low
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// automatically when the operation
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// is complete. The complement of
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// this bit is output as
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// interrupts[1]. After a reset,
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// the run bit is always set to 1b.
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// Depending on the option, program
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// ROM or program RAM, the
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// following applies: Program ROM -
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// The first sequencer instruction
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// sets the bit to 0b. This is done
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// immediately after the hardware
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// reset is released. Program RAM -
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// The sequencer must set the bit
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// to 0b. As a valid firmware may
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// not have been loaded, the
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// sequencer is held in software
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// reset after the hardware reset
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// is released (the reset bit in
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// PKA_SEQ_CRTL is set to 1b).
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// After the FW image is loaded and
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// the Reset bit is cleared, the
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// sequencer starts to execute the
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// FW. The first instruction clears
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// the run bit. In both cases a few
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// clock cycles are needed before
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// the first instruction is
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// executed and the run bit state
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// has been propagated.
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#define PKA_FUNCTION_RUN_M 0x00008000
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#define PKA_FUNCTION_RUN_S 15
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#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M \
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0x00007000 // These bits select the complex
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// sequencer operation to perform:
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// 000b: None 001b: ExpMod-CRT
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// 010b: ExpMod-ACT4 (compatible
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// with EIP2315) 011b: ECC-ADD (if
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// available in firmware, otherwise
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// reserved) 100b: ExpMod-ACT2
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// (compatible with EIP2316) 101b:
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// ECC-MUL (if available in
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// firmware, otherwise reserved)
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// 110b: ExpMod-variable 111b:
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// ModInv (if available in
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// firmware, otherwise reserved)
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// The encoding of these operations
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// is determined by sequencer
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// firmware.
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#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12
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#define PKA_FUNCTION_COPY 0x00000800 // Perform copy operation
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#define PKA_FUNCTION_COPY_M 0x00000800
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#define PKA_FUNCTION_COPY_S 11
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#define PKA_FUNCTION_COMPARE 0x00000400 // Perform compare operation
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#define PKA_FUNCTION_COMPARE_M 0x00000400
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#define PKA_FUNCTION_COMPARE_S 10
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#define PKA_FUNCTION_MODULO 0x00000200 // Perform modulo operation
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#define PKA_FUNCTION_MODULO_M 0x00000200
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#define PKA_FUNCTION_MODULO_S 9
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#define PKA_FUNCTION_DIVIDE 0x00000100 // Perform divide operation
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#define PKA_FUNCTION_DIVIDE_M 0x00000100
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#define PKA_FUNCTION_DIVIDE_S 8
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#define PKA_FUNCTION_LSHIFT 0x00000080 // Perform left shift operation
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#define PKA_FUNCTION_LSHIFT_M 0x00000080
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#define PKA_FUNCTION_LSHIFT_S 7
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#define PKA_FUNCTION_RSHIFT 0x00000040 // Perform right shift operation
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#define PKA_FUNCTION_RSHIFT_M 0x00000040
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#define PKA_FUNCTION_RSHIFT_S 6
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#define PKA_FUNCTION_SUBTRACT 0x00000020 // Perform subtract operation
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#define PKA_FUNCTION_SUBTRACT_M 0x00000020
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#define PKA_FUNCTION_SUBTRACT_S 5
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#define PKA_FUNCTION_ADD 0x00000010 // Perform add operation
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#define PKA_FUNCTION_ADD_M 0x00000010
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#define PKA_FUNCTION_ADD_S 4
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#define PKA_FUNCTION_MS_ONE 0x00000008 // Loads the location of the Most
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// Significant one bit within the
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// result word indicated in the
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// PKA_MSW register into bits [4:0]
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// of the PKA_DIVMSW register - can
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// only be used with basic PKCP
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// operations, except for Divide,
|
|
// Modulo and Compare.
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|
#define PKA_FUNCTION_MS_ONE_M 0x00000008
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#define PKA_FUNCTION_MS_ONE_S 3
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#define PKA_FUNCTION_ADDSUB 0x00000002 // Perform combined add/subtract
|
|
// operation
|
|
#define PKA_FUNCTION_ADDSUB_M 0x00000002
|
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#define PKA_FUNCTION_ADDSUB_S 1
|
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#define PKA_FUNCTION_MULTIPLY 0x00000001 // Perform multiply operation
|
|
#define PKA_FUNCTION_MULTIPLY_M 0x00000001
|
|
#define PKA_FUNCTION_MULTIPLY_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_COMPARE register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_COMPARE_A_GREATER_THAN_B \
|
|
0x00000004 // Vector_A is greater than
|
|
// Vector_B
|
|
|
|
#define PKA_COMPARE_A_GREATER_THAN_B_M \
|
|
0x00000004
|
|
#define PKA_COMPARE_A_GREATER_THAN_B_S 2
|
|
#define PKA_COMPARE_A_LESS_THAN_B \
|
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0x00000002 // Vector_A is less than Vector_B
|
|
|
|
#define PKA_COMPARE_A_LESS_THAN_B_M \
|
|
0x00000002
|
|
#define PKA_COMPARE_A_LESS_THAN_B_S 1
|
|
#define PKA_COMPARE_A_EQUALS_B 0x00000001 // Vector_A is equal to Vector_B
|
|
#define PKA_COMPARE_A_EQUALS_B_M \
|
|
0x00000001
|
|
#define PKA_COMPARE_A_EQUALS_B_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_MSW register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_MSW_RESULT_IS_ZERO 0x00008000 // The result vector is all
|
|
// zeroes, ignore the address
|
|
// returned in bits [10:0]
|
|
#define PKA_MSW_RESULT_IS_ZERO_M \
|
|
0x00008000
|
|
#define PKA_MSW_RESULT_IS_ZERO_S 15
|
|
#define PKA_MSW_MSW_ADDRESS_M 0x000007FF // Address of the most-significant
|
|
// nonzero 32-bit word of the
|
|
// result vector in PKA RAM
|
|
#define PKA_MSW_MSW_ADDRESS_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_DIVMSW register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_DIVMSW_RESULT_IS_ZERO \
|
|
0x00008000 // The result vector is all
|
|
// zeroes, ignore the address
|
|
// returned in bits [10:0]
|
|
|
|
#define PKA_DIVMSW_RESULT_IS_ZERO_M \
|
|
0x00008000
|
|
#define PKA_DIVMSW_RESULT_IS_ZERO_S 15
|
|
#define PKA_DIVMSW_MSW_ADDRESS_M \
|
|
0x000007FF // Address of the most significant
|
|
// nonzero 32-bit word of the
|
|
// remainder result vector in PKA
|
|
// RAM
|
|
|
|
#define PKA_DIVMSW_MSW_ADDRESS_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_SEQ_CTRL register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_SEQ_CTRL_RESET 0x80000000 // Option program ROM: Reset value
|
|
// = 0. Read/Write, reset value 0b
|
|
// (ZERO). Writing 1b resets the
|
|
// sequencer, write to 0b to
|
|
// restart operations again. As the
|
|
// reset value is 0b, the sequencer
|
|
// will automatically start
|
|
// operations executing from
|
|
// program ROM. This bit should
|
|
// always be written with zero and
|
|
// ignored when reading this
|
|
// register. Option Program RAM:
|
|
// Reset value =1. Read/Write,
|
|
// reset value 1b (ONE). When 1b,
|
|
// the sequencer is held in a reset
|
|
// state and the PKA_PROGRAM area
|
|
// is accessible for loading the
|
|
// sequencer program (while the
|
|
// PKA_DATA_RAM is inaccessible),
|
|
// write to 0b to (re)start
|
|
// sequencer operations and disable
|
|
// PKA_PROGRAM area accessibility
|
|
// (also enables the PKA_DATA_RAM
|
|
// accesses). Resetting the
|
|
// sequencer (in order to load
|
|
// other firmware) should only be
|
|
// done when the PKA Engine is not
|
|
// performing any operations (i.e.
|
|
// the run bit in the PKA_FUNCTION
|
|
// register should be zero).
|
|
#define PKA_SEQ_CTRL_RESET_M 0x80000000
|
|
#define PKA_SEQ_CTRL_RESET_S 31
|
|
#define PKA_SEQ_CTRL_SEQUENCER_STATUS_M \
|
|
0x0000FF00 // These read-only bits can be
|
|
// used by the sequencer to
|
|
// communicate status to the
|
|
// outside world. Bit [8] is also
|
|
// used as sequencer interrupt,
|
|
// with the complement of this bit
|
|
// ORed into the run bit in
|
|
// PKA_FUNCTION. This field should
|
|
// always be written with zeroes
|
|
// and ignored when reading this
|
|
// register.
|
|
|
|
#define PKA_SEQ_CTRL_SEQUENCER_STATUS_S 8
|
|
#define PKA_SEQ_CTRL_SW_CONTROL_STATUS_M \
|
|
0x000000FF // These bits can be used by
|
|
// software to trigger sequencer
|
|
// operations. External logic can
|
|
// set these bits by writing 1b,
|
|
// cannot reset them by writing 0b.
|
|
// The sequencer can reset these
|
|
// bits by writing 0b, cannot set
|
|
// them by writing 1b. Setting the
|
|
// run bit in PKA_FUNCTION together
|
|
// with a nonzero sequencer
|
|
// operations field automatically
|
|
// sets bit [0] here. This field
|
|
// should always be written with
|
|
// zeroes and ignored when reading
|
|
// this register.
|
|
|
|
#define PKA_SEQ_CTRL_SW_CONTROL_STATUS_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_OPTIONS register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_M \
|
|
0xFF000000 // Number of words in the first
|
|
// LNME's FIFO RAM Should be
|
|
// ignored if LNME configuration is
|
|
// 0. The contents of this field
|
|
// indicate the actual depth as
|
|
// selected by the LNME FIFO RAM
|
|
// size strap input, fifo_size_sel.
|
|
// Note: Reset value is undefined
|
|
|
|
#define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_S 24
|
|
#define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_M \
|
|
0x003F0000 // Number of processing elements
|
|
// in the pipeline of the first
|
|
// LNME Should be ignored if LNME
|
|
// configuration is 0. Note: Reset
|
|
// value is undefined.
|
|
|
|
#define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_S 16
|
|
#define PKA_OPTIONS_MMM3A 0x00001000 // Reserved for a future
|
|
// functional extension to the LNME
|
|
// Always 0b
|
|
#define PKA_OPTIONS_MMM3A_M 0x00001000
|
|
#define PKA_OPTIONS_MMM3A_S 12
|
|
#define PKA_OPTIONS_INT_MASKING 0x00000800 // Value 0b indicates that the
|
|
// main interrupt output (bit [1]
|
|
// of the interrupts output bus) is
|
|
// the direct complement of the run
|
|
// bit in the PKA_CONTROL register,
|
|
// value 1b indicates that
|
|
// interrupt masking logic is
|
|
// present for this output. Note:
|
|
// Reset value is undefined
|
|
#define PKA_OPTIONS_INT_MASKING_M \
|
|
0x00000800
|
|
#define PKA_OPTIONS_INT_MASKING_S 11
|
|
#define PKA_OPTIONS_PROTECTION_OPTION_M \
|
|
0x00000700 // Value 0 indicates no additional
|
|
// protection against side channel
|
|
// attacks, value 1 indicates the
|
|
// SCAP option, value 3 indicates
|
|
// the PROT option; other values
|
|
// are reserved. Note: Reset value
|
|
// is undefined
|
|
|
|
#define PKA_OPTIONS_PROTECTION_OPTION_S 8
|
|
#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 // Value 1b indicates sequencer
|
|
// program storage in RAM, value 0b
|
|
// in ROM. Note: Reset value is
|
|
// undefined
|
|
#define PKA_OPTIONS_PROGRAM_RAM_M \
|
|
0x00000080
|
|
#define PKA_OPTIONS_PROGRAM_RAM_S 7
|
|
#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M \
|
|
0x00000060 // Value 1 indicates a standard
|
|
// sequencer; other values are
|
|
// reserved.
|
|
|
|
#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5
|
|
#define PKA_OPTIONS_LNME_CONFIGURATION_M \
|
|
0x0000001C // Value 0 indicates NO LNME,
|
|
// value 1 indicates one standard
|
|
// LNME (with alpha = 32, beta =
|
|
// 8); other values reserved. Note:
|
|
// Reset value is undefined
|
|
|
|
#define PKA_OPTIONS_LNME_CONFIGURATION_S 2
|
|
#define PKA_OPTIONS_PKCP_CONFIGURATION_M \
|
|
0x00000003 // Value 1 indicates a PKCP with a
|
|
// 16x16 multiplier, value 2
|
|
// indicates a PKCP with a 32x32
|
|
// multiplier, other values
|
|
// reserved. Note: Reset value is
|
|
// undefined.
|
|
|
|
#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_SW_REV register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_SW_REV_FW_CAPABILITIES_M \
|
|
0xF0000000 // 4-bit binary encoding for the
|
|
// functionality implemented in the
|
|
// firmware. Value 0 indicates
|
|
// basic ModExp with/without CRT.
|
|
// Value 1 adds Modular Inversion,
|
|
// value 2 adds Modular Inversion
|
|
// and ECC operations. Values 3-15
|
|
// are reserved.
|
|
|
|
#define PKA_SW_REV_FW_CAPABILITIES_S 28
|
|
#define PKA_SW_REV_MAJOR_FW_REVISION_M \
|
|
0x0F000000 // 4-bit binary encoding of the
|
|
// major firmware revision number
|
|
|
|
#define PKA_SW_REV_MAJOR_FW_REVISION_S 24
|
|
#define PKA_SW_REV_MINOR_FW_REVISION_M \
|
|
0x00F00000 // 4-bit binary encoding of the
|
|
// minor firmware revision number
|
|
|
|
#define PKA_SW_REV_MINOR_FW_REVISION_S 20
|
|
#define PKA_SW_REV_FW_PATCH_LEVEL_M \
|
|
0x000F0000 // 4-bit binary encoding of the
|
|
// firmware patch level, initial
|
|
// release will carry value zero
|
|
// Patches are used to remove bugs
|
|
// without changing the
|
|
// functionality or interface of a
|
|
// module.
|
|
|
|
#define PKA_SW_REV_FW_PATCH_LEVEL_S 16
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PKA_REVISION register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PKA_REVISION_MAJOR_HW_REVISION_M \
|
|
0x0F000000 // 4-bit binary encoding of the
|
|
// major hardware revision number
|
|
|
|
#define PKA_REVISION_MAJOR_HW_REVISION_S 24
|
|
#define PKA_REVISION_MINOR_HW_REVISION_M \
|
|
0x00F00000 // 4-bit binary encoding of the
|
|
// minor hardware revision number
|
|
|
|
#define PKA_REVISION_MINOR_HW_REVISION_S 20
|
|
#define PKA_REVISION_HW_PATCH_LEVEL_M \
|
|
0x000F0000 // 4-bit binary encoding of the
|
|
// hardware patch level, initial
|
|
// release will carry value zero
|
|
// Patches are used to remove bugs
|
|
// without changing the
|
|
// functionality or interface of a
|
|
// module.
|
|
|
|
#define PKA_REVISION_HW_PATCH_LEVEL_S 16
|
|
#define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_M \
|
|
0x0000FF00 // Bit-by-bit logic complement of
|
|
// bits [7:0], EIP-28 gives 0xE3
|
|
|
|
#define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8
|
|
#define PKA_REVISION_BASIC_EIP_NUMBER_M \
|
|
0x000000FF // 8-bit binary encoding of the
|
|
// EIP number, EIP-28 gives 0x1C
|
|
|
|
#define PKA_REVISION_BASIC_EIP_NUMBER_S 0
|
|
|
|
|
|
#endif // __HW_PKA_H__
|
|
|