mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
e246c19fe1
Rework SPI periph driver to use proper RIOT GPIO API functions.
Also cleanup header files by using vendor defines and remove
obsolete code. Further, adapt board config accordingly.
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cc2538
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* @{
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*
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* @file
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* @brief CC2538 SSI interface
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*
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* @author Ian Martin <ian@locicontrols.com>
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* @author Sebastian Meiling <s@mlng.net>
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*/
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#ifndef CC2538_SSI_H
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#define CC2538_SSI_H
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#include "cc2538.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief SSI component registers
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*/
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typedef struct {
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cc2538_reg_t CR0; /**< SSI Control Register 0 */
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cc2538_reg_t CR1; /**< SSI Control Register 1 */
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cc2538_reg_t DR; /**< SSI Data register */
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cc2538_reg_t SR; /**< SSI FIFO/busy Status Register */
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cc2538_reg_t CPSR; /**< SSI Clock Register */
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cc2538_reg_t IM; /**< SSI Interrupt Mask register */
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cc2538_reg_t RIS; /**< SSI Raw Interrupt Status register */
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cc2538_reg_t MIS; /**< SSI Masked Interrupt Status register */
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cc2538_reg_t ICR; /**< SSI Interrupt Clear Register */
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cc2538_reg_t DMACTL; /**< SSI uDMA Control Register. */
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cc2538_reg_t CC; /**< SSI clock configuration */
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} cc2538_ssi_t;
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/**
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* @brief Set CR0 data size (bits)
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*/
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#define SSI_CR0_DSS(x) (x - 1)
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/**
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* @brief Define CC register bitfields
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* @{
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*/
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#define SSI_CC_CS_SYSDIV (0x0)
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#define SSI_CC_CS_IODIV (0x1)
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#define SSI_CC_CS_DSEN (0x4)
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/** @} */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC2538_SSI_H */
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/** @} */
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