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https://github.com/RIOT-OS/RIOT.git
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280 lines
15 KiB
C
280 lines
15 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_cc2538_rfcore CC2538 RF core interface
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* @ingroup cpu_cc2538_regs
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* @{
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*
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* @file
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* @brief CC2538 RF core interface
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*
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* @author Ian Martin <ian@locicontrols.com>
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*
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*/
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#ifndef CC2538_RFCORE_H
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#define CC2538_RFCORE_H
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#include "cc2538.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief RF Core component registers
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*/
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typedef struct {
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cc2538_reg_t FFSM_SRCRESMASK0; /**< RF Source address matching result */
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cc2538_reg_t FFSM_SRCRESMASK1; /**< RF Source address matching result */
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cc2538_reg_t FFSM_SRCRESMASK2; /**< RF Source address matching result */
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cc2538_reg_t FFSM_SRCRESINDEX; /**< RF Source address matching result */
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cc2538_reg_t FFSM_SRCEXTPENDEN0; /**< RF Source address matching control */
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cc2538_reg_t FFSM_SRCEXTPENDEN1; /**< RF Source address matching control */
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cc2538_reg_t FFSM_SRCEXTPENDEN2; /**< RF Source address matching control */
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cc2538_reg_t FFSM_SRCSHORTPENDEN0; /**< RF Source address matching control */
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cc2538_reg_t FFSM_SRCSHORTPENDEN1; /**< RF Source address matching control */
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cc2538_reg_t FFSM_SRCSHORTPENDEN2; /**< RF Source address matching control */
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cc2538_reg_t FFSM_EXT_ADDR0; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR1; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR2; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR3; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR4; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR5; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR6; /**< RF Local address information */
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cc2538_reg_t FFSM_EXT_ADDR7; /**< RF Local address information */
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cc2538_reg_t FFSM_PAN_ID0; /**< RF Local address information */
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cc2538_reg_t FFSM_PAN_ID1; /**< RF Local address information */
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cc2538_reg_t FFSM_SHORT_ADDR0; /**< RF Local address information */
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cc2538_reg_t FFSM_SHORT_ADDR1; /**< RF Local address information */
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cc2538_reg_t RESERVED1[10]; /**< Reserved bytes */
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union {
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cc2538_reg_t XREG_FRMFILT0; /**< RF Frame Filter 0 */
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struct {
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cc2538_reg_t FRAME_FILTER_EN : 1;
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cc2538_reg_t PAN_COORDINATOR : 1;
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cc2538_reg_t MAX_FRAME_VERSION: 2;
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cc2538_reg_t RESERVED : 28;
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} XREG_FRMFILT0bits;
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};
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cc2538_reg_t XREG_FRMFILT1; /**< RF Frame Filter 1 */
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cc2538_reg_t XREG_SRCMATCH; /**< RF Source address matching and pending bits */
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cc2538_reg_t XREG_SRCSHORTEN0; /**< RF Short address matching */
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cc2538_reg_t XREG_SRCSHORTEN1; /**< RF Short address matching */
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cc2538_reg_t XREG_SRCSHORTEN2; /**< RF Short address matching */
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cc2538_reg_t XREG_SRCEXTEN0; /**< RF Extended address matching */
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cc2538_reg_t XREG_SRCEXTEN1; /**< RF Extended address matching */
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cc2538_reg_t XREG_SRCEXTEN2; /**< RF Extended address matching */
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union {
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cc2538_reg_t XREG_FRMCTRL0; /**< RF Frame handling */
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struct {
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cc2538_reg_t TX_MODE : 2;
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cc2538_reg_t RX_MODE : 2;
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cc2538_reg_t ENERGY_SCAN : 1;
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cc2538_reg_t AUTOACK : 1;
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cc2538_reg_t AUTOCRC : 1;
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cc2538_reg_t APPEND_DATA_MODE : 1;
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cc2538_reg_t RESERVED : 24;
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} XREG_FRMCTRL0bits;
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};
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cc2538_reg_t XREG_FRMCTRL1; /**< RF Frame handling */
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cc2538_reg_t XREG_RXENABLE; /**< RF RX enabling */
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cc2538_reg_t XREG_RXMASKSET; /**< RF RX enabling */
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cc2538_reg_t XREG_RXMASKCLR; /**< RF RX disabling */
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cc2538_reg_t XREG_FREQTUNE; /**< RF Crystal oscillator frequency tuning */
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cc2538_reg_t XREG_FREQCTRL; /**< RF Controls the RF frequency */
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cc2538_reg_t XREG_TXPOWER; /**< RF Controls the output power */
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cc2538_reg_t XREG_TXCTRL; /**< RF Controls the TX settings */
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union {
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cc2538_reg_t XREG_FSMSTAT0; /**< RF Radio status register */
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struct {
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cc2538_reg_t FSM_FFCTRL_STATE : 6;
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cc2538_reg_t CAL_RUNNING : 1;
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cc2538_reg_t CAL_DONE : 1;
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cc2538_reg_t RESERVED : 24;
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} XREG_FSMSTAT0bits;
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};
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union {
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cc2538_reg_t XREG_FSMSTAT1; /**< RF Radio status register */
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struct {
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cc2538_reg_t RX_ACTIVE : 1;
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cc2538_reg_t TX_ACTIVE : 1;
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cc2538_reg_t LOCK_STATUS : 1;
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cc2538_reg_t SAMPLED_CCA : 1;
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cc2538_reg_t CCA : 1;
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cc2538_reg_t SFD : 1;
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cc2538_reg_t FIFOP : 1;
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cc2538_reg_t FIFO : 1;
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cc2538_reg_t RESERVED : 24;
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} XREG_FSMSTAT1bits;
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};
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cc2538_reg_t XREG_FIFOPCTRL; /**< RF FIFOP threshold */
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cc2538_reg_t XREG_FSMCTRL; /**< RF FSM options */
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cc2538_reg_t XREG_CCACTRL0; /**< RF CCA threshold */
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cc2538_reg_t XREG_CCACTRL1; /**< RF Other CCA Options */
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cc2538_reg_t XREG_RSSI; /**< RF RSSI status register */
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/**
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* @brief RSSI status register
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*/
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union {
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cc2538_reg_t XREG_RSSISTAT; /**< RF RSSI valid status register */
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struct {
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cc2538_reg_t RSSI_VALID : 1; /**< RSSI value is valid */
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cc2538_reg_t RESERVED : 31; /**< Reserved bits */
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} XREG_RSSISTATbits;
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};
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cc2538_reg_t XREG_RXFIRST; /**< RF First byte in RX FIFO */
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cc2538_reg_t XREG_RXFIFOCNT; /**< RF Number of bytes in RX FIFO */
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cc2538_reg_t XREG_TXFIFOCNT; /**< RF Number of bytes in TX FIFO */
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cc2538_reg_t XREG_RXFIRST_PTR; /**< RF RX FIFO pointer */
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cc2538_reg_t XREG_RXLAST_PTR; /**< RF RX FIFO pointer */
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cc2538_reg_t XREG_RXP1_PTR; /**< RF RX FIFO pointer */
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cc2538_reg_t RESERVED2; /**< Reserved bytes */
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cc2538_reg_t XREG_TXFIRST_PTR; /**< RF TX FIFO pointer */
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cc2538_reg_t XREG_TXLAST_PTR; /**< RF TX FIFO pointer */
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cc2538_reg_t XREG_RFIRQM0; /**< RF interrupt masks */
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cc2538_reg_t XREG_RFIRQM1; /**< RF interrupt masks */
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cc2538_reg_t XREG_RFERRM; /**< RF error interrupt mask */
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cc2538_reg_t RESERVED3; /**< Reserved bytes */
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/**
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* @brief RF random data register
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*/
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union {
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cc2538_reg_t XREG_RFRND; /**< RF Random data */
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struct {
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cc2538_reg_t IRND : 1; /**< Random bit from the I channel of the receiver */
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cc2538_reg_t QRND : 1; /**< Random bit from the Q channel of the receiver */
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cc2538_reg_t RESERVED : 30; /**< Reserved bits */
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} XREG_RFRNDbits;
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};
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cc2538_reg_t XREG_MDMCTRL0; /**< RF Controls modem */
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cc2538_reg_t XREG_MDMCTRL1; /**< RF Controls modem */
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cc2538_reg_t XREG_FREQEST; /**< RF Estimated RF frequency offset */
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cc2538_reg_t XREG_RXCTRL; /**< RF Tune receive section */
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cc2538_reg_t XREG_FSCTRL; /**< RF Tune frequency synthesizer */
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cc2538_reg_t XREG_FSCAL0; /**< RF Tune frequency calibration */
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cc2538_reg_t XREG_FSCAL1; /**< RF Tune frequency calibration */
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cc2538_reg_t XREG_FSCAL2; /**< RF Tune frequency calibration */
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cc2538_reg_t XREG_FSCAL3; /**< RF Tune frequency calibration */
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cc2538_reg_t XREG_AGCCTRL0; /**< RF AGC dynamic range control */
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cc2538_reg_t XREG_AGCCTRL1; /**< RF AGC reference level */
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cc2538_reg_t XREG_AGCCTRL2; /**< RF AGC gain override */
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cc2538_reg_t XREG_AGCCTRL3; /**< RF AGC control */
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cc2538_reg_t XREG_ADCTEST0; /**< RF ADC tuning */
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cc2538_reg_t XREG_ADCTEST1; /**< RF ADC tuning */
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cc2538_reg_t XREG_ADCTEST2; /**< RF ADC tuning */
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cc2538_reg_t XREG_MDMTEST0; /**< RF Test register for modem */
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cc2538_reg_t XREG_MDMTEST1; /**< RF Test Register for Modem */
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cc2538_reg_t XREG_DACTEST0; /**< RF DAC override value */
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cc2538_reg_t XREG_DACTEST1; /**< RF DAC override value */
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cc2538_reg_t XREG_DACTEST2; /**< RF DAC test setting */
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cc2538_reg_t XREG_ATEST; /**< RF Analog test control */
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cc2538_reg_t XREG_PTEST0; /**< RF Override power-down register */
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cc2538_reg_t XREG_PTEST1; /**< RF Override power-down register */
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cc2538_reg_t RESERVED4[32]; /**< Reserved bytes */
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cc2538_reg_t XREG_CSPCTRL; /**< RF CSP control bit */
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cc2538_reg_t XREG_CSPSTAT; /**< RF CSP status register */
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cc2538_reg_t XREG_CSPX; /**< RF CSP X data register */
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cc2538_reg_t XREG_CSPY; /**< RF CSP Y data register */
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cc2538_reg_t XREG_CSPZ; /**< RF CSP Z data register */
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cc2538_reg_t XREG_CSPT; /**< RF CSP T data register */
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cc2538_reg_t RESERVED5[5]; /**< Reserved bytes */
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cc2538_reg_t XREG_RFC_OBS_CTRL0; /**< RF observation mux control */
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cc2538_reg_t XREG_RFC_OBS_CTRL1; /**< RF observation mux control */
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cc2538_reg_t XREG_RFC_OBS_CTRL2; /**< RF observation mux control */
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cc2538_reg_t RESERVED6[12]; /**< Reserved bytes */
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cc2538_reg_t XREG_TXFILTCFG; /**< RF TX filter configuration */
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cc2538_reg_t RESERVED7[5]; /**< Reserved bytes */
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cc2538_reg_t SFR_MTCSPCFG; /**< RF MAC Timer event configuration */
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cc2538_reg_t SFR_MTCTRL; /**< RF MAC Timer control register */
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cc2538_reg_t SFR_MTIRQM; /**< RF MAC Timer interrupt mask */
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cc2538_reg_t SFR_MTIRQF; /**< RF MAC Timer interrupt flags */
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cc2538_reg_t SFR_MTMSEL; /**< RF MAC Timer multiplex select */
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cc2538_reg_t SFR_MTM0; /**< RF MAC Timer multiplexed register 0 */
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cc2538_reg_t SFR_MTM1; /**< RF MAC Timer multiplexed register 1 */
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cc2538_reg_t SFR_MTMOVF2; /**< RF MAC Timer multiplexed overflow register 2 */
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cc2538_reg_t SFR_MTMOVF1; /**< RF MAC Timer multiplexed overflow register 1 */
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cc2538_reg_t SFR_MTMOVF0; /**< RF MAC Timer multiplexed overflow register 0 */
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cc2538_reg_t SFR_RFDATA; /**< RF Tx/Rx FIFO */
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cc2538_reg_t SFR_RFERRF; /**< RF error interrupt flags */
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cc2538_reg_t SFR_RFIRQF1; /**< RF interrupt flags */
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cc2538_reg_t SFR_RFIRQF0; /**< RF interrupt flags */
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cc2538_reg_t SFR_RFST; /**< RF CSMA-CA/strobe processor */
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} cc2538_rfcore_t;
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#define RFCORE ( (cc2538_rfcore_t*)0x40088580 ) /**< RF Core instance */
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/** @brief RF Core opcodes */
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enum {
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DECZ = 0xc5, /**< Decrement Z */
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DECY = 0xc4, /**< Decrement Y */
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DECX = 0xc3, /**< Decrement X */
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INCZ = 0xc2, /**< Increment Z */
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INCY = 0xc1, /**< Increment Y */
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INCX = 0xc0, /**< Increment X */
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INCMAXY = 0xc8, /**< Increment Y not greater than M. | M (M = 0-7) */
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RANDXY = 0xbd, /**< Load random value into X. */
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INT = 0xba, /**< Interrupt */
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WAITX = 0xbc, /**< Wait for X MAC timer overflows */
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SETCMP1 = 0xbe, /**< Set the compare value of the MAC timer to the current timer value. */
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WAIT_W = 0x80, /**< Wait for W MAC timer overflows | W (W = 0-31) */
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WEVENT1 = 0xb8, /**< Wait until MAC timer event 1 */
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WEVENT2 = 0xb9, /**< Wait until MAC timer event 2 */
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LABEL = 0xbb, /**< Set loop label */
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RPT_C = 0xa0, /**< Conditional repeat | N | C (N = 0, 8; C = 0-7) */
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SKIP_S_C = 0x00, /**< Conditional skip instruction | S | N | C */
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STOP = 0xd2, /**< Stop program execution */
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SNOP = 0xd0, /**< No operation */
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SRXON = 0xd3, /**< Enable and calibrate frequency synthesizer for RX */
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STXON = 0xd9, /**< Enable TX after calibration */
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STXONCCA = 0xda, /**< Enable calibration and TX if CCA indicates a clear channel */
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SSAMPLECCA = 0xdb, /**< Sample the current CCA value to SAMPLED_CCA */
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SRFOFF = 0xdf, /**< Disable RX or TX and frequency synthesizer. */
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SFLUSHRX = 0xdd, /**< Flush RX FIFO buffer and reset demodulator */
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SFLUSHTX = 0xde, /**< Flush TX FIFO buffer */
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SACK = 0xd6, /**< Send acknowledge frame with pending field cleared */
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SACKPEND = 0xd7, /**< Send acknowledge frame with the pending field set */
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SNACK = 0xd8, /**< Abort sending of acknowledge frame */
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SRXMASKBITSET = 0xd4, /**< Set bit in RXENABLE register */
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SRXMASKBITCLR = 0xd5, /**< Clear bit in RXENABLE register */
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ISSTOP = 0xe2, /**< Stop program execution */
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ISSTART = 0xe1, /**< Start program execution */
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ISRXON = 0xe3, /**< Enable and calibrate frequency synthesizer for RX */
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ISRXMASKBITSET = 0xe4, /**< Set bit in RXENABLE */
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ISRXMASKBITCLR = 0xe5, /**< Clear bit in RXENABLE */
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ISTXON = 0xe9, /**< Enable TX after calibration */
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ISTXONCCA = 0xea, /**< Enable calibration and TX if CCA indicates a clear channel */
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ISSAMPLECCA = 0xeb, /**< Sample the current CCA value to SAMPLED_CCA */
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ISRFOFF = 0xef, /**< Disable RX or TX, and the frequency synthesizer. */
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ISFLUSHRX = 0xed, /**< Flush RX FIFO buffer and reset demodulator */
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ISFLUSHTX = 0xee, /**< Flush TX FIFO buffer */
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ISACK = 0xe6, /**< Send acknowledge frame with the pending field cleared */
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ISACKPEND = 0xe7, /**< Send acknowledge frame with the pending field set */
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ISNACK = 0xe8, /**< Abort sending of acknowledge frame */
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ISCLEAR = 0xff, /**< Clear CSP program memory, reset program counter */
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};
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif /* CC2538_RFCORE_H */
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/** @} */
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