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95 lines
1.6 KiB
C
95 lines
1.6 KiB
C
/*
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* Copyright (C) 2023 HAW Hamburg. All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @ingroup cpu_arm7tdmi_gba
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*
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* @{
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*/
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/**
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* @file
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* @brief ARM7TDMI_GBA CPU configuration
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*
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* @author
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*/
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/**
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* @brief This arch uses the inlined irq API.
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*/
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#define IRQ_API_INLINED (1)
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/**
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* @name Kernel configuration
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* @{
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*/
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#define THREAD_EXTRA_STACKSIZE_PRINTF (512)
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#ifndef THREAD_STACKSIZE_DEFAULT
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#define THREAD_STACKSIZE_DEFAULT (1024)
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#endif
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#ifndef THREAD_STACKSIZE_IDLE
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#define THREAD_STACKSIZE_IDLE (160)
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#endif
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/** @} */
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/**
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* @brief Stack size used for the undefined instruction interrupt stack
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*/
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#define UND_STACKSIZE (64)
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/**
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* @brief Stack size used for the abort interrupt stack
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*/
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#define ABT_STACKSIZE (64)
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/**
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* @brief Stack size used for the interrupt (ISR) stack
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*/
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#ifndef ISR_STACKSIZE
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#define ISR_STACKSIZE (400)
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#endif
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/**
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* @brief Stack size used for the fast interrupt (FIQ) stack
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*/
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#define FIQ_STACKSIZE (64)
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/**
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* @brief Stack size used for the supervisor mode (SVC) stack
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*/
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#define SVC_STACKSIZE (400)
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/**
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* @brief Stack size used for the user mode/kernel init stack
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*/
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#define USR_STACKSIZE (4096)
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/**
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* @brief The CPU has 2 blocks of SRAM at different addresses.
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* (primary on-chip RAM and external working EWRAM)
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*/
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#define NUM_HEAPS (2)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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