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RIOT/boards/slstk3401a/include/periph_conf.h
Karl Fessel c41342dc5b boards/*efm32*: do not force RTT_FREQUENCY
while keeping a sane (rtt shared with rtc (counter)) default
this commit adds the ability to define RTT_FREQUENCY
to some thing different than 1 Hz
2021-04-20 11:12:45 +02:00

216 lines
4.4 KiB
C

/*
* Copyright (C) 2015-2020 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_slstk3401a
* @{
*
* @file
* @brief Configuration of CPU peripherals for the SLSTK3401A starter kit
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Bas Stottelaar <basstottelaar@gmail.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "cpu.h"
#include "periph_cpu.h"
#include "em_cmu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock configuration
* @{
*/
#ifndef CLOCK_HF
#define CLOCK_HF cmuSelect_HFXO
#endif
#ifndef CLOCK_CORE_DIV
#define CLOCK_CORE_DIV cmuClkDiv_1
#endif
#ifndef CLOCK_LFA
#define CLOCK_LFA cmuSelect_LFXO
#endif
#ifndef CLOCK_LFB
#define CLOCK_LFB cmuSelect_LFXO
#endif
#ifndef CLOCK_LFE
#define CLOCK_LFE cmuSelect_LFXO
#endif
/** @} */
/**
* @name DC-DC configuration
* @{
*/
#ifdef EMU_DCDCINIT_OFF
#error "This option will soft-brick your board. Please remove it."
#endif
/** @} */
/**
* @name ADC configuration
* @{
*/
static const adc_conf_t adc_config[] = {
{
.dev = ADC0,
.cmu = cmuClock_ADC0,
}
};
static const adc_chan_conf_t adc_channel_config[] = {
{
.dev = 0,
.input = adcPosSelTEMP,
.reference = adcRef1V25,
.acq_time = adcAcqTime8
},
{
.dev = 0,
.input = adcPosSelAVDD,
.reference = adcRef5V,
.acq_time = adcAcqTime8
}
};
#define ADC_DEV_NUMOF ARRAY_SIZE(adc_config)
#define ADC_NUMOF ARRAY_SIZE(adc_channel_config)
/** @} */
/**
* @name I2C configuration
* @{
*/
static const i2c_conf_t i2c_config[] = {
{
.dev = I2C0,
.sda_pin = GPIO_PIN(PC, 10),
.scl_pin = GPIO_PIN(PC, 11),
.loc = I2C_ROUTELOC0_SDALOC_LOC15 |
I2C_ROUTELOC0_SCLLOC_LOC15,
.cmu = cmuClock_I2C0,
.irq = I2C0_IRQn,
.speed = I2C_SPEED_NORMAL
}
};
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
#define I2C_0_ISR isr_i2c0
/** @} */
/**
* @name RTT configuration
* @{
*/
#ifndef RTT_FREQUENCY
#define RTT_FREQUENCY (1U) /* in Hz */
#endif
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_dev_t spi_config[] = {
{
.dev = USART1,
.mosi_pin = GPIO_PIN(PC, 6),
.miso_pin = GPIO_PIN(PC, 7),
.clk_pin = GPIO_PIN(PC, 8),
.loc = USART_ROUTELOC0_RXLOC_LOC11 |
USART_ROUTELOC0_TXLOC_LOC11 |
USART_ROUTELOC0_CLKLOC_LOC11,
.cmu = cmuClock_USART1,
.irq = USART1_RX_IRQn
}
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
/**
* @name Timer configuration
*
* The implementation uses two timers in cascade mode.
* @{
*/
static const timer_conf_t timer_config[] = {
{
.prescaler = {
.dev = TIMER0,
.cmu = cmuClock_TIMER0
},
.timer = {
.dev = TIMER1,
.cmu = cmuClock_TIMER1
},
.irq = TIMER1_IRQn,
.channel_numof = 3
},
{
.prescaler = {
.dev = NULL,
.cmu = cmuClock_LETIMER0
},
.timer = {
.dev = LETIMER0,
.cmu = cmuClock_LETIMER0
},
.irq = LETIMER0_IRQn,
.channel_numof = 2
}
};
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
#define TIMER_0_ISR isr_timer1
#define TIMER_1_ISR isr_letimer0
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART0,
.rx_pin = GPIO_PIN(PA, 1),
.tx_pin = GPIO_PIN(PA, 0),
.loc = USART_ROUTELOC0_RXLOC_LOC0 |
USART_ROUTELOC0_TXLOC_LOC0,
.cmu = cmuClock_USART0,
.irq = USART0_RX_IRQn
},
{
.dev = LEUART0,
.rx_pin = GPIO_PIN(PD, 11),
.tx_pin = GPIO_PIN(PD, 10),
.loc = LEUART_ROUTELOC0_RXLOC_LOC18 |
LEUART_ROUTELOC0_TXLOC_LOC18,
.cmu = cmuClock_LEUART0,
.irq = LEUART0_IRQn
}
};
#define UART_NUMOF ARRAY_SIZE(uart_config)
#define UART_0_ISR_RX isr_usart0_rx
#define UART_1_ISR_RX isr_leuart0
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */