mirror of
https://github.com/RIOT-OS/RIOT.git
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05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
165 lines
4.0 KiB
C
165 lines
4.0 KiB
C
/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_ek-lm4f120xl
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the ek-lm4f120xl board
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "macros/units.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Define the nominal CPU core clock in this board
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* @{
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*/
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#define CLK80 1
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#define CLK50 2
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#define CLK40 3
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#define CLK16 4
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#define CLK1 5
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#define CLOCK_SOURCE CLK40
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#define CLOCK_CORECLOCK MHZ(80)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = WTIMER0_BASE,
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.max = 0xffffffff,
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.irqn = Timer0A_IRQn,
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.sysctl = SYSCTL_PERIPH_WTIMER0,
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.intbase = INT_WTIMER0A,
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.channels = 1
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},
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{
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.dev = WTIMER1_BASE,
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.max = 0xffffffff,
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.irqn = Timer1A_IRQn,
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.sysctl = SYSCTL_PERIPH_WTIMER1,
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.intbase = INT_WTIMER1A,
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.channels = 1
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},
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};
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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#define TIMER_0_ISR isr_wtimer0a
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#define TIMER_1_ISR isr_wtimer1a
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_IRQ_PRIO 1
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/* UART clock runs with 40MHz */
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#define UART_CLK ROM_SysCtlClockGet()
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/* UART 0 device configuration */
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#define UART_0_DEV UART0_BASE
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#define UART_0_CLK (40000000)
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#define UART_0_IRQ_CHAN UART0_IRQn
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#define UART_0_ISR isr_uart0
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_TX_PIN UART_PA1_U0TX
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#define UART_0_RX_PIN UART_PA0_U0RX
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (12)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_confs[] = {
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{
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.ssi_sysctl = SYSCTL_PERIPH_SSI0,
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.ssi_base = SSI0_BASE,
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.gpio_sysctl = SYSCTL_PERIPH_GPIOA,
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.gpio_port = GPIO_PORTA_BASE,
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.pins = {
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.clk = GPIO_PA2_SSI0CLK,
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.fss = GPIO_PA3_SSI0FSS,
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.rx = GPIO_PA4_SSI0RX,
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.tx = GPIO_PA5_SSI0TX,
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.mask = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5
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}
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},
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{
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.ssi_sysctl = SYSCTL_PERIPH_SSI1,
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.ssi_base = SSI1_BASE,
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.gpio_sysctl = SYSCTL_PERIPH_GPIOF,
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.gpio_port = GPIO_PORTF_BASE,
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.pins = {
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.clk = GPIO_PF2_SSI1CLK,
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.fss = GPIO_PF3_SSI1FSS,
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.rx = GPIO_PF0_SSI1RX,
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.tx = GPIO_PF1_SSI1TX,
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.mask = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3
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}
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},
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{
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.ssi_sysctl = SYSCTL_PERIPH_SSI2,
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.ssi_base = SSI2_BASE,
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.gpio_sysctl = SYSCTL_PERIPH_GPIOB,
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.gpio_port = GPIO_PORTB_BASE,
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.pins = {
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.clk = GPIO_PB4_SSI2CLK,
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.fss = GPIO_PB5_SSI2FSS,
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.rx = GPIO_PB6_SSI2RX,
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.tx = GPIO_PB7_SSI2TX,
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.mask = GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7
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}
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},
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{
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.ssi_sysctl = SYSCTL_PERIPH_SSI3,
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.ssi_base = SSI3_BASE,
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.gpio_sysctl = SYSCTL_PERIPH_GPIOD,
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.gpio_port = GPIO_PORTD_BASE,
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.pins = {
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.clk = GPIO_PD0_SSI3CLK,
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.fss = GPIO_PD1_SSI3FSS,
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.rx = GPIO_PD2_SSI3RX,
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.tx = GPIO_PD3_SSI3TX,
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.mask = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3
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}
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_confs)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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