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190 lines
10 KiB
C
190 lines
10 KiB
C
/**
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* \file
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*
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* \brief Component description for TRNG
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_TRNG_COMPONENT_
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#define _SAML21_TRNG_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR TRNG */
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/* ========================================================================== */
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/** \addtogroup SAML21_TRNG True Random Generator */
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/*@{*/
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#define TRNG_U2242
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#define REV_TRNG 0x100
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/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t :1; /*!< bit: 0 Reserved */
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uint8_t ENABLE:1; /*!< bit: 1 Enable */
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uint8_t :4; /*!< bit: 2.. 5 Reserved */
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uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
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uint8_t :1; /*!< bit: 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_CTRLA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */
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#define TRNG_CTRLA_RESETVALUE 0x00ul /**< \brief (TRNG_CTRLA reset_value) Control A */
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#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */
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#define TRNG_CTRLA_ENABLE (0x1ul << TRNG_CTRLA_ENABLE_Pos)
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#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */
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#define TRNG_CTRLA_RUNSTDBY (0x1ul << TRNG_CTRLA_RUNSTDBY_Pos)
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#define TRNG_CTRLA_MASK 0x42ul /**< \brief (TRNG_CTRLA) MASK Register */
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/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_EVCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */
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#define TRNG_EVCTRL_RESETVALUE 0x00ul /**< \brief (TRNG_EVCTRL reset_value) Event Control */
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#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
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#define TRNG_EVCTRL_DATARDYEO (0x1ul << TRNG_EVCTRL_DATARDYEO_Pos)
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#define TRNG_EVCTRL_MASK 0x01ul /**< \brief (TRNG_EVCTRL) MASK Register */
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/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_INTENCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
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#define TRNG_INTENCLR_RESETVALUE 0x00ul /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
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#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
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#define TRNG_INTENCLR_DATARDY (0x1ul << TRNG_INTENCLR_DATARDY_Pos)
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#define TRNG_INTENCLR_MASK 0x01ul /**< \brief (TRNG_INTENCLR) MASK Register */
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/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_INTENSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
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#define TRNG_INTENSET_RESETVALUE 0x00ul /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
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#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
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#define TRNG_INTENSET_DATARDY (0x1ul << TRNG_INTENSET_DATARDY_Pos)
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#define TRNG_INTENSET_MASK 0x01ul /**< \brief (TRNG_INTENSET) MASK Register */
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/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_INTFLAG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
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#define TRNG_INTFLAG_RESETVALUE 0x00ul /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
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#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
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#define TRNG_INTFLAG_DATARDY (0x1ul << TRNG_INTFLAG_DATARDY_Pos)
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#define TRNG_INTFLAG_MASK 0x01ul /**< \brief (TRNG_INTFLAG) MASK Register */
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/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t DATA:32; /*!< bit: 0..31 Output Data */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} TRNG_DATA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */
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#define TRNG_DATA_RESETVALUE 0x00000000ul /**< \brief (TRNG_DATA reset_value) Output Data */
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#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */
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#define TRNG_DATA_DATA_Msk (0xFFFFFFFFul << TRNG_DATA_DATA_Pos)
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#define TRNG_DATA_DATA(value) ((TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos)))
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#define TRNG_DATA_MASK 0xFFFFFFFFul /**< \brief (TRNG_DATA) MASK Register */
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/** \brief TRNG hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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RoReg8 Reserved1[0x3];
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__IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
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RoReg8 Reserved2[0x3];
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__IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
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__IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
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__IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
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RoReg8 Reserved3[0x15];
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__I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
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} Trng;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAML21_TRNG_COMPONENT_ */
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