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158 lines
3.6 KiB
C
158 lines
3.6 KiB
C
/*
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* Copyright (C) 2015 Jan Wagner <mail@jwagner.eu>
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* 2015-2016 Freie Universität Berlin
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* 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf5x_common
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* @ingroup drivers_periph_gpio_ll
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* @{
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*
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* @file
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* @brief CPU specific part of the Peripheral GPIO Low-Level API
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*
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* @note This GPIO driver implementation supports only one pin to be
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* defined as external interrupt.
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*
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* @author Christian Kühling <kuehling@zedat.fu-berlin.de>
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* @author Timo Ziegler <timo.ziegler@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Jan Wagner <mail@jwagner.eu>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef GPIO_LL_ARCH_H
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#define GPIO_LL_ARCH_H
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#include <assert.h>
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#include "cpu.h"
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#include "irq.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN /* hide implementation specific details from Doxygen */
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#define PORT_BIT (1 << 5)
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#define PIN_MASK (0x1f)
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#define NRF5X_IO_AREA_START (0x40000000UL)
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/* Compatibility wrapper defines for nRF9160 */
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#ifdef NRF_P0_S
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#define NRF_P0 NRF_P0_S
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#endif
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#if defined(CPU_FAM_NRF51)
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#define GPIO_PORT(num) ((gpio_port_t)NRF_GPIO)
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#define GPIO_PORT_NUM(port) 0
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#elif defined(NRF_P1)
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#define GPIO_PORT(num) ((num) ? (gpio_port_t)NRF_P1 : (gpio_port_t)NRF_P0)
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#define GPIO_PORT_NUM(port) ((port == (gpio_port_t)NRF_P1) ? 1 : 0)
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#else
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#define GPIO_PORT(num) ((gpio_port_t)NRF_P0)
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#define GPIO_PORT_NUM(port) 0
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#endif
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static inline uword_t gpio_ll_read(gpio_port_t port)
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{
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NRF_GPIO_Type *p = (NRF_GPIO_Type *)port;
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return p->IN;
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}
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static inline uword_t gpio_ll_read_output(gpio_port_t port)
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{
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NRF_GPIO_Type *p = (NRF_GPIO_Type *)port;
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return p->OUT;
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}
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static inline void gpio_ll_set(gpio_port_t port, uword_t mask)
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{
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NRF_GPIO_Type *p = (NRF_GPIO_Type *)port;
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p->OUTSET = mask;
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}
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static inline void gpio_ll_clear(gpio_port_t port, uword_t mask)
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{
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NRF_GPIO_Type *p = (NRF_GPIO_Type *)port;
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p->OUTCLR = mask;
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}
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static inline void gpio_ll_toggle(gpio_port_t port, uword_t mask)
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{
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NRF_GPIO_Type *p = (NRF_GPIO_Type *)port;
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unsigned state = irq_disable();
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p->OUT ^= mask;
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irq_restore(state);
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}
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static inline void gpio_ll_write(gpio_port_t port, uword_t value)
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{
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NRF_GPIO_Type *p = (NRF_GPIO_Type *)port;
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p->OUT = value;
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}
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static inline gpio_port_t gpio_get_port(gpio_t pin)
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{
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#if defined(NRF_P1)
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return GPIO_PORT(pin >> 5);
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#else
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(void)pin;
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return GPIO_PORT(0);
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#endif
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}
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static inline uint8_t gpio_get_pin_num(gpio_t pin)
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{
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#if defined(NRF_P1)
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return pin & PIN_MASK;
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#else
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return (uint8_t)pin;
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#endif
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}
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static inline gpio_port_t gpio_port_pack_addr(void *addr)
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{
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return (gpio_port_t)addr;
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}
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static inline void * gpio_port_unpack_addr(gpio_port_t port)
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{
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/* NRF5X_IO_AREA_START is the start of the memory mapped I/O area. Both data
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* and flash are mapped before it. So if it is an I/O address, it
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* cannot be a packed data address and (hopefully) is a GPIO port */
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if (port >= NRF5X_IO_AREA_START) {
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return NULL;
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}
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return (void *)port;
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}
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static inline bool is_gpio_port_num_valid(uint_fast8_t num)
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{
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switch (num) {
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default:
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return false;
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case 0:
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#if defined(NRF_P1)
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case 1:
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#endif
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return true;
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}
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}
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#endif /* DOXYGEN */
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_LL_ARCH_H */
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/** @} */
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