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https://github.com/RIOT-OS/RIOT.git
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323 lines
6.9 KiB
C
323 lines
6.9 KiB
C
/*
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* Copyright (C) 2015 HAW Hamburg
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* 2016 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atmega_common
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation for ATmega family
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*
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* @author René Herthel <rene-herthel@outlook.de>
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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* @author Laurent Navet <laurent.navet@gmail.com>
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*
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* @}
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*/
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#include <stdio.h>
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#include <avr/interrupt.h>
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#include "cpu.h"
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#include "periph/gpio.h"
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#include "periph_conf.h"
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#define GPIO_BASE_PORT_A (0x20)
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#define GPIO_OFFSET_PORT_H (0xCB)
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#define GPIO_OFFSET_PIN_PORT (0x02)
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#define GPIO_OFFSET_PIN_PIN (0x03)
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/*
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* @brief Define GPIO interruptions for an specific atmega CPU, by default
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* 2 (for small atmega CPUs)
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*/
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#if defined(INT2_vect)
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#define GPIO_EXT_INT_NUMOF (3U)
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#elif defined(INT3_vect)
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#define GPIO_EXT_INT_NUMOF (4U)
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#elif defined(INT4_vect)
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#define GPIO_EXT_INT_NUMOF (4U)
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#elif defined(INT5_vect)
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#define GPIO_EXT_INT_NUMOF (4U)
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#elif defined(INT6_vect)
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#define GPIO_EXT_INT_NUMOF (4U)
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#elif defined(INT7_vect)
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#define GPIO_EXT_INT_NUMOF (4U)
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#else
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#define GPIO_EXT_INT_NUMOF (2U)
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#endif
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static gpio_isr_ctx_t config[GPIO_EXT_INT_NUMOF];
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/**
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* @brief Extract the pin number of the given pin
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*/
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static inline uint8_t _pin_num(gpio_t pin)
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{
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return (pin & 0x0f);
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}
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/**
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* @brief Extract the port number of the given pin
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*/
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static inline uint8_t _port_num(gpio_t pin)
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{
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return (pin >> 4) & 0x0f;
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}
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/**
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* @brief Generate the PORTx address of the give pin.
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*/
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static inline uint16_t _port_addr(gpio_t pin)
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{
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uint8_t port_num = _port_num(pin);
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uint16_t port_addr = port_num * GPIO_OFFSET_PIN_PIN;
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port_addr += GPIO_BASE_PORT_A;
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port_addr += GPIO_OFFSET_PIN_PORT;
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#if defined (PORTG)
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if (port_num > PORT_G) {
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port_addr += GPIO_OFFSET_PORT_H;
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}
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#endif
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return port_addr;
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}
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/**
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* @brief Generate the DDRx address of the given pin
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*/
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static inline uint16_t _ddr_addr(gpio_t pin)
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{
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return (_port_addr(pin) - 0x01);
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}
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/**
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* @brief Generate the PINx address of the given pin.
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*/
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static inline uint16_t _pin_addr(gpio_t pin)
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{
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return (_port_addr(pin) - 0x02);
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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switch (mode) {
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case GPIO_OUT:
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_SFR_MEM8(_ddr_addr(pin)) |= (1 << _pin_num(pin));
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break;
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case GPIO_IN:
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_SFR_MEM8(_ddr_addr(pin)) &= ~(1 << _pin_num(pin));
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_SFR_MEM8(_port_addr(pin)) &= ~(1 << _pin_num(pin));
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break;
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case GPIO_IN_PU:
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_SFR_MEM8(_port_addr(pin)) |= (1 << _pin_num(pin));
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break;
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default:
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return -1;
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}
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return 0;
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}
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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uint8_t pin_num = _pin_num(pin);
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if ((_port_num(pin) == PORT_D && pin_num > 3)
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#if defined (PORTE)
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|| (_port_num(pin) == PORT_E && pin_num < 4)
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|| (_port_num(pin) != PORT_D && _port_num(pin) != PORT_E)
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#elif defined(CPU_ATMEGA328P)
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|| (pin_num < 2) || (_port_num(pin) != PORT_D)
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#elif defined(CPU_ATMEGA1284P)
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|| (_port_num(pin) == PORT_B && pin_num != 2)
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|| (_port_num(pin) == PORT_D && pin_num < 2)
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|| (_port_num(pin) != PORT_D && _port_num(pin) != PORT_D)
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#endif
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|| ((mode != GPIO_IN) && (mode != GPIO_IN_PU))) {
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return -1;
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}
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gpio_init(pin, mode);
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/* clear global interrupt flag */
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cli();
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#if defined(CPU_ATMEGA328P)
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/* INT pins start at PD2 instead of at PD0 */
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pin_num -= 2;
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#elif defined(CPU_ATMEGA1284P)
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/* INT pins start at PD2 instead of at PD0 on PORT_D */
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if (_port_num(pin) == PORT_D) {
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pin_num -= 2;
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}
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#endif
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EIMSK |= (1 << pin_num);
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/* configure the flank */
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if (flank > GPIO_RISING) {
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return -1;
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}
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if (pin_num < 4) {
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EICRA |= (flank << (pin_num * 2));
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}
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#if defined(EICRB)
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else {
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EICRB |= (flank << (pin_num * 2) % 4);
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}
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#endif
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/* set callback */
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config[pin_num].cb = cb;
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config[pin_num].arg = arg;
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/* set global interrupt flag */
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sei();
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return 0;
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}
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void gpio_irq_enable(gpio_t pin)
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{
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#if defined(CPU_ATMEGA328P)
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/* INT pins start at PD2 instead of at PD0 */
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EIMSK |= (1 << (_pin_num(pin) - 2));
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#elif defined(CPU_ATMEGA1284P)
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/* INT pins start at PD2 instead of at PD0 on PORT_D */
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if (_port_num(pin) == PORT_D) {
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EIMSK |= (1 << (_pin_num(pin) - 2));
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}
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else {
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EIMSK |= (1 << _pin_num(pin));
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}
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#else
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EIMSK |= (1 << _pin_num(pin));
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#endif
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}
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void gpio_irq_disable(gpio_t pin)
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{
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#if defined(CPU_ATMEGA328P)
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/* INT pins start at PD2 instead of at PD0 */
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EIMSK &= ~(1 << (_pin_num(pin) - 2));
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#elif defined (CPU_ATMEGA1284P)
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/* INT pins start at PD2 instead of at PD0 on PORT_D */
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if (_port_num(pin) == PORT_D) {
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EIMSK &= ~(1 << (_pin_num(pin) - 2));
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}
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else {
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EIMSK &= ~(1 << _pin_num(pin));
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}
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#else
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EIMSK &= ~(1 << _pin_num(pin));
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#endif
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}
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int gpio_read(gpio_t pin)
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{
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return (_SFR_MEM8(_pin_addr(pin)) & (1 << _pin_num(pin)));
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}
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void gpio_set(gpio_t pin)
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{
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_SFR_MEM8(_port_addr(pin)) |= (1 << _pin_num(pin));
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}
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void gpio_clear(gpio_t pin)
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{
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_SFR_MEM8(_port_addr(pin)) &= ~(1 << _pin_num(pin));
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}
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void gpio_toggle(gpio_t pin)
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{
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if (gpio_read(pin)) {
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gpio_clear(pin);
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}
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else {
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gpio_set(pin);
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}
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value) {
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gpio_set(pin);
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}
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else {
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gpio_clear(pin);
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}
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}
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static inline void irq_handler(uint8_t pin_num)
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{
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__enter_isr();
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config[pin_num].cb(config[pin_num].arg);
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__exit_isr();
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}
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ISR(INT0_vect, ISR_BLOCK)
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{
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irq_handler(0); /**< predefined interrupt pin */
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}
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ISR(INT1_vect, ISR_BLOCK)
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{
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irq_handler(1); /**< predefined interrupt pin */
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}
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#if defined(INT2_vect)
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ISR(INT2_vect, ISR_BLOCK)
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{
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irq_handler(2); /**< predefined interrupt pin */
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}
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#endif
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#if defined(INT3_vect)
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ISR(INT3_vect, ISR_BLOCK)
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{
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irq_handler(3); /**< predefined interrupt pin */
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}
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#endif
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#if defined(INT4_vect)
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ISR(INT4_vect, ISR_BLOCK)
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{
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irq_handler(4); /**< predefined interrupt pin */
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}
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#endif
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#if defined(INT5_vect)
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ISR(INT5_vect, ISR_BLOCK)
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{
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irq_handler(5); /**< predefined interrupt pin */
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}
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#endif
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#if defined(INT6_vect)
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ISR(INT6_vect, ISR_BLOCK)
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{
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irq_handler(6); /**< predefined interrupt pin */
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}
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#endif
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#if defined(INT7_vect) && !defined(BOARD_JIMINY_MEGA256RFR2)
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/**< INT7 is context swap pin for the Jiminy board */
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ISR(INT7_vect, ISR_BLOCK)
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{
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irq_handler(7); /**< predefined interrupt pin */
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}
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#endif /* INT7_vect && END BOARD_JIMINY_MEGA256RFR2 */
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