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https://github.com/RIOT-OS/RIOT.git
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158 lines
4.2 KiB
C
158 lines
4.2 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_nucleo-l1
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-l1 board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR (isr_tim5)
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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/**
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* @brief UART configuration
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_CLK (CLOCK_CORECLOCK) /* UART clock runs with 32MHz (F_CPU / 1) */
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#define UART_0_IRQ USART2_IRQn
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#define UART_0_ISR isr_usart2
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#define UART_0_BUS_FREQ 32000000
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/* UART 0 pin configuration */
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#define UART_0_RX_PIN GPIO_PIN(PORT_A, 3)
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#define UART_0_TX_PIN GPIO_PIN(PORT_A, 2)
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#define UART_0_AF GPIO_AF7
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_ISR isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_PORT GPIOA
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#define SPI_0_PIN_SCK 5
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#define SPI_0_PIN_MOSI 7
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#define SPI_0_PIN_MISO 6
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#define SPI_0_PIN_AF 5
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_0_EN 1
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#define I2C_1_EN 1
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#define I2C_NUMOF (I2C_0_EN + I2C_1_EN)
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 1 device configuration */
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#define I2C_1_EVT_ISR isr_i2c2_ev
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#define I2C_1_ERR_ISR isr_i2c2_er
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static const i2c_conf_t i2c_config[] = {
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/* device, port, scl-, sda-pin-number, I2C-AF, ER-IRQn, EV-IRQn */
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{I2C1, GPIO_PIN(PORT_B, 8), GPIO_PIN(PORT_B, 9), GPIO_OD_PU,
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GPIO_AF4, I2C1_ER_IRQn, I2C1_EV_IRQn},
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{I2C2, GPIO_PIN(PORT_B, 10), GPIO_PIN(PORT_B, 11), GPIO_OD_PU,
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GPIO_AF4, I2C2_ER_IRQn, I2C2_EV_IRQn},
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};
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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