Benjamin Valentin 4095eac9f2 cpu: mips32r2_common: set BITARITHM_HAS_CLZ ... The MIPS ISA implements CLZ: https://ti.tuwien.ac.at/cps/teaching/courses/cavo/files/MIPS32-IS.pdf For `tests/periph_gpio` this shaves off 20 bytes on `6lowpan-clicker`.		2021-02-02 11:14:38 +01:00
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architecture_arch.h	cpu/mips32r2_common: Add architecture_arch.h	2020-09-29 12:34:00 +02:00
atomic_utils_arch.h	cpu/*/atomic_utils_arch.h: Add volatile qualifier	2020-11-24 14:00:52 +01:00
c11_atomics_compat_cpu.hpp	cpu: Platform specific C11 atomics compat headers	2019-10-24 23:08:36 +02:00
cpu.h	cpu: mips32r2_common: set BITARITHM_HAS_CLZ	2021-02-02 11:14:38 +01:00
eic.h	cpu: mips: Refactor EIC	2020-03-25 19:10:01 +00:00
thread_arch.h	cpu/mips32r2_common: Inline thread_yield_higher function	2021-01-19 11:03:21 +01:00