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https://github.com/RIOT-OS/RIOT.git
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319 lines
9.0 KiB
C
319 lines
9.0 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include "periph/gpio.h"
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#include "periph/spi.h"
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#include "lis3dh.h"
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/**
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* @ingroup drivers_lis3dh
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* @{
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*
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* @file
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* @brief Implementation of LIS3DH SPI driver
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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static inline int lis3dh_write_bits(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t mask,
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const uint8_t values);
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static int lis3dh_write_reg(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t value);
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static int lis3dh_read_regs(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t len,
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uint8_t *buf);
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int lis3dh_init(lis3dh_t *dev, spi_t spi, gpio_t cs_pin, gpio_t int1_pin, gpio_t int2_pin, uint8_t scale)
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{
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uint8_t in;
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dev->spi = spi;
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dev->cs = cs_pin;
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dev->int1 = int1_pin;
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dev->int2 = int2_pin;
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dev->scale = 0;
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/* CS */
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gpio_init(dev->cs, GPIO_DIR_OUT, GPIO_NOPULL);
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gpio_set(dev->cs);
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if (lis3dh_read_regs(dev, LIS3DH_REG_WHO_AM_I, 1, &in) < 0) {
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/* Communication error */
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return -1;
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}
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if (in != LIS3DH_WHO_AM_I_RESPONSE) {
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/* Chip is not responding correctly */
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return -1;
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}
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/* Clear all settings */
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lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG1, LIS3DH_CTRL_REG1_XYZEN_MASK);
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/* Disable HP filter */
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lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG2, 0);
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/* Disable INT1 interrupt sources */
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lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG3, 0);
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/* Set block data update and little endian, set Normal mode (LP=0, HR=1) */
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lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG4,
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(LIS3DH_CTRL_REG4_BDU_ENABLE |
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LIS3DH_CTRL_REG4_BLE_LITTLE_ENDIAN |
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LIS3DH_CTRL_REG4_HR_MASK));
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/* Disable FIFO */
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lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG5, 0);
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/* Reset INT2 settings */
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lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG6, 0);
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/* Configure scale */
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lis3dh_set_scale(dev, scale);
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/* Initialize the interrupt pins */
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gpio_init(dev->int1, GPIO_DIR_IN, GPIO_NOPULL);
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gpio_init(dev->int2, GPIO_DIR_IN, GPIO_NOPULL);
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return 0;
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}
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int lis3dh_read_xyz(const lis3dh_t *dev, lis3dh_data_t *acc_data)
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{
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uint8_t i;
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/* Set READ MULTIPLE mode */
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static const uint8_t addr = (LIS3DH_REG_OUT_X_L | LIS3DH_SPI_READ_MASK | LIS3DH_SPI_MULTI_MASK);
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi);
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/* Perform the transaction */
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gpio_clear(dev->cs);
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if (spi_transfer_regs(dev->spi, addr, NULL, (char *)acc_data,
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sizeof(lis3dh_data_t)) != sizeof(lis3dh_data_t)) {
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/* Transfer error */
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gpio_set(dev->cs);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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return -1;
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}
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gpio_set(dev->cs);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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/* Scale to milli-G */
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for (i = 0; i < 3; ++i) {
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int32_t tmp = (int32_t)(((int16_t *)acc_data)[i]);
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tmp *= dev->scale;
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tmp /= 32768;
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(((int16_t *)acc_data)[i]) = (int16_t)tmp;
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}
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return 0;
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}
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int lis3dh_read_aux_adc1(const lis3dh_t *dev, int16_t *out)
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{
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return lis3dh_read_regs(dev, LIS3DH_REG_OUT_AUX_ADC1_L, LIS3DH_ADC_DATA_SIZE, (uint8_t *)out);
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}
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int lis3dh_read_aux_adc2(const lis3dh_t *dev, int16_t *out)
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{
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return lis3dh_read_regs(dev, LIS3DH_REG_OUT_AUX_ADC2_L, LIS3DH_ADC_DATA_SIZE, (uint8_t *)out);
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}
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int lis3dh_read_aux_adc3(const lis3dh_t *dev, int16_t *out)
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{
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return lis3dh_read_regs(dev, LIS3DH_REG_OUT_AUX_ADC3_L, LIS3DH_ADC_DATA_SIZE, (uint8_t *)out);
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}
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int lis3dh_set_aux_adc(lis3dh_t *dev, const uint8_t enable, const uint8_t temperature)
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{
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return lis3dh_write_bits(dev, LIS3DH_REG_TEMP_CFG_REG, LIS3DH_TEMP_CFG_REG_ADC_PD_MASK,
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(enable ? LIS3DH_TEMP_CFG_REG_ADC_PD_MASK : 0) |
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(temperature ? LIS3DH_TEMP_CFG_REG_TEMP_EN_MASK : 0));
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}
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int lis3dh_set_axes(lis3dh_t *dev, const uint8_t axes)
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{
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return lis3dh_write_bits(dev, LIS3DH_REG_CTRL_REG1, LIS3DH_CTRL_REG1_XYZEN_MASK, axes);
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}
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int lis3dh_set_fifo(lis3dh_t *dev, const uint8_t mode, const uint8_t watermark)
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{
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int status;
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uint8_t reg;
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reg = (watermark << LIS3DH_FIFO_CTRL_REG_FTH_SHIFT)
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& LIS3DH_FIFO_CTRL_REG_FTH_MASK;
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reg |= mode;
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status = lis3dh_write_reg(dev, LIS3DH_REG_FIFO_CTRL_REG, reg);
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if (status < 0) {
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/* communication error */
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return status;
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}
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if (mode != 0x00) {
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status = lis3dh_write_bits(dev, LIS3DH_REG_CTRL_REG5,
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LIS3DH_CTRL_REG5_FIFO_EN_MASK, LIS3DH_CTRL_REG5_FIFO_EN_MASK);
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} else {
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status = lis3dh_write_bits(dev, LIS3DH_REG_CTRL_REG5,
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LIS3DH_CTRL_REG5_FIFO_EN_MASK, 0);
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}
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return status;
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}
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int lis3dh_set_odr(lis3dh_t *dev, const uint8_t odr)
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{
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return lis3dh_write_bits(dev, LIS3DH_REG_CTRL_REG1,
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LIS3DH_CTRL_REG1_ODR_MASK, odr);
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}
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int lis3dh_set_scale(lis3dh_t *dev, const uint8_t scale)
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{
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/* Sensor full range is -32768 -- +32767 (measurements are left adjusted) */
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/* => Scale factor is scale/32768 */
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switch (scale)
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{
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case LIS3DH_SCALE_2G:
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dev->scale = 2000;
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break;
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case LIS3DH_SCALE_4G:
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dev->scale = 4000;
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break;
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case LIS3DH_SCALE_8G:
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dev->scale = 8000;
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break;
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case LIS3DH_SCALE_16G:
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dev->scale = 16000;
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break;
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default:
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return -1;
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}
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return lis3dh_write_bits(dev, LIS3DH_REG_CTRL_REG4, LIS3DH_CTRL_REG4_FS_MASK,
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scale);
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}
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int lis3dh_set_int1(lis3dh_t *dev, const uint8_t mode)
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{
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return lis3dh_write_reg(dev, LIS3DH_REG_CTRL_REG3, mode);
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}
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int lis3dh_get_fifo_level(lis3dh_t *dev)
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{
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uint8_t reg;
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int level;
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if (lis3dh_read_regs(dev, LIS3DH_REG_FIFO_SRC_REG, 1, ®) != 0) {
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return -1;
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}
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level = (reg & LIS3DH_FIFO_SRC_REG_FSS_MASK) >> LIS3DH_FIFO_SRC_REG_FSS_SHIFT;
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return level;
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}
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/**
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* @brief Read sequential registers from the LIS3DH.
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*
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* @param[in] dev Device descriptor
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* @param[in] reg The source register starting address
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* @param[in] len Number of bytes to read
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* @param[out] buf The values of the source registers will be written here
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*
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* @return 0 on success
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* @return -1 on error
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*/
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static int lis3dh_read_regs(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t len,
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uint8_t *buf)
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{
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/* Set READ MULTIPLE mode */
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uint8_t addr = (reg & LIS3DH_SPI_ADDRESS_MASK) | LIS3DH_SPI_READ_MASK | LIS3DH_SPI_MULTI_MASK;
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi);
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/* Perform the transaction */
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gpio_clear(dev->cs);
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if (spi_transfer_regs(dev->spi, addr, NULL, (char *)buf, len) < 0) {
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/* Transfer error */
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gpio_set(dev->cs);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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return -1;
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}
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gpio_set(dev->cs);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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return 0;
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}
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/**
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* @brief Write a value to an 8 bit register in the LIS3DH.
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*
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* @param[in] reg The target register.
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* @param[in] value The value to write.
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*
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* @return 0 on success
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* @return -1 on error
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*/
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static int lis3dh_write_reg(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t value)
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{
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/* Set WRITE SINGLE mode */
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uint8_t addr = (reg & LIS3DH_SPI_ADDRESS_MASK) | LIS3DH_SPI_WRITE_MASK | LIS3DH_SPI_SINGLE_MASK;
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi);
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/* Perform the transaction */
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gpio_clear(dev->cs);
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if (spi_transfer_reg(dev->spi, addr, value, NULL) < 0) {
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/* Transfer error */
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gpio_set(dev->cs);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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return -1;
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}
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gpio_set(dev->cs);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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return 0;
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}
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/**
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* @brief Write (both set and clear) bits of an 8-bit register on the LIS3DH.
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*
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* @param[in] addr Register address on the LIS3DH.
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* @param[in] mask Bitmask for the bits to modify.
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* @param[in] values The values to write to the masked bits.
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*
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* @return 0 on success
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* @return -1 on error
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*/
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static inline int
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lis3dh_write_bits(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t mask,
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const uint8_t values)
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{
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uint8_t tmp;
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if (lis3dh_read_regs(dev, reg, 1, &tmp) < 0) {
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/* Communication error */
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return -1;
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}
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tmp &= ~mask;
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tmp |= (values & mask);
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if (lis3dh_write_reg(dev, reg, tmp) < 0) {
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/* Communication error */
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return -1;
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}
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return 0;
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}
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/** @} */
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