mirror of
https://github.com/RIOT-OS/RIOT.git
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236 lines
6.9 KiB
C
236 lines
6.9 KiB
C
/*
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* Copyright (C) 2014 Baptiste CLENET
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_saml21
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* @{
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* @file
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* @brief Low-level RTC driver implementation
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* @author Baptiste Clenet <baptiste.clenet@xsoen.com>
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* @autor ported to SAML21 by FWX <FWX@dialine.fr>
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* @}
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*/
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#include <time.h>
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#include "cpu.h"
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#include "periph/rtc.h"
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#include "periph_conf.h"
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/* guard file in case no RTC device was specified */
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#if RTC_NUMOF
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typedef struct {
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rtc_alarm_cb_t cb; /**< callback called from RTC interrupt */
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void *arg; /**< argument passed to the callback */
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} rtc_state_t;
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static rtc_state_t rtc_callback;
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/* At 1Hz, RTC goes till 63 years (2^5, see 17.8.22 in datasheet)
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* reference_year is set to 100 (offset) to be in our current time (2000)
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* Thanks to this, the user will be able to set time in 2000's*/
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static uint16_t reference_year = 100;
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void rtc_init(void)
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{
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/* Turn on power manager for RTC */
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/* Already done in cpu_init() */
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/* MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC; */
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/* DISABLE RTC MASTER */
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rtc_poweroff();
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#if EXTERNAL_OSC32_SOURCE
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/* RTC uses External 32,768KHz Oscillator */
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OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_XTALEN
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| OSC32KCTRL_XOSC32K_EN1K
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| OSC32KCTRL_XOSC32K_RUNSTDBY
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| OSC32KCTRL_OSC32K_ENABLE;
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/* Wait XOSC32K Ready */
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while (OSC32KCTRL->STATUS.bit.XOSC32KRDY==0);
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/* RTC source clock is external oscillator at 1kHz */
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K;
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#endif /* EXTERNAL_OSC32_SOURCE */
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#if INTERNAL_OSC32_SOURCE
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uint32_t * pCalibrationArea;
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uint32_t osc32kcal;
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/* Read OSC32KCAL, calibration data for OSC32 !!! */
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pCalibrationArea = (uint32_t*) NVMCTRL_OTP5;
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osc32kcal = ( (*pCalibrationArea) & 0x1FC0 ) >> 6;
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/* RTC use Low Power Internal Oscillator at 1kHz */
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OSC32KCTRL->OSC32K.reg = OSC32KCTRL_OSC32K_RUNSTDBY
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| OSC32KCTRL_OSC32K_EN1K
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| OSC32KCTRL_OSC32K_CALIB(osc32kcal)
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| OSC32KCTRL_OSC32K_ENABLE;
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/* Wait OSC32K Ready */
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while (OSC32KCTRL->STATUS.bit.OSC32KRDY==0);
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/* RTC uses internal 32,768KHz Oscillator */
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K;
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#endif /* INTERNAL_OSC32_SOURCE */
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#if ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE
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/* RTC uses Ultra Low Power internal 32,768KHz Oscillator */
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K;
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#endif /* ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE */
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/* Software Reset the RTC */
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RTC->MODE2.CTRLA.bit.SWRST = 1;
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/* Wait end of reset */
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while (RTC->MODE2.CTRLA.bit.SWRST);
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/* RTC config with RTC_MODE2_CTRL_CLKREP = 0 (24h) */
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RTC->MODE2.CTRLA.reg = RTC_MODE2_CTRLA_PRESCALER_DIV1024 | /* CLK_RTC_CNT = 1KHz / 1024 -> 1Hz */
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RTC_MODE2_CTRLA_MODE_CLOCK | /* Mode 2: Clock/Calendar */
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RTC_MODE2_CTRLA_SYNCDIS; /* Clock Read Synchronization Enable */
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/* Clear interrupt flags */
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RTC->MODE2.INTFLAG.bit.OVF = 1;
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RTC->MODE2.INTFLAG.bit.ALARM0 = 1;
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rtc_poweron();
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}
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int rtc_set_time(struct tm *time)
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{
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if ((time->tm_year < reference_year) || (time->tm_year > reference_year + 63)) {
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return -1;
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}
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else {
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while (RTC->MODE2.SYNCBUSY.bit.CLOCK);
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RTC->MODE2.CLOCK.reg = RTC_MODE2_CLOCK_YEAR(time->tm_year - reference_year)
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| RTC_MODE2_CLOCK_MONTH(time->tm_mon + 1)
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| RTC_MODE2_CLOCK_DAY(time->tm_mday)
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| RTC_MODE2_CLOCK_HOUR(time->tm_hour)
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| RTC_MODE2_CLOCK_MINUTE(time->tm_min)
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| RTC_MODE2_CLOCK_SECOND(time->tm_sec);
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while (RTC->MODE2.SYNCBUSY.bit.CLOCK);
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}
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return 0;
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}
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int rtc_get_time(struct tm *time)
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{
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RTC_MODE2_CLOCK_Type clock;
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/* Read register in one time */
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clock.reg = RTC->MODE2.CLOCK.reg;
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time->tm_year = clock.bit.YEAR + reference_year;
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if ((time->tm_year < reference_year) || (time->tm_year > (reference_year + 63))) {
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return -1;
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}
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time->tm_mon = clock.bit.MONTH - 1;
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time->tm_mday = clock.bit.DAY;
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time->tm_hour = clock.bit.HOUR;
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time->tm_min = clock.bit.MINUTE;
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time->tm_sec = clock.bit.SECOND;
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return 0;
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}
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int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
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{
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rtc_clear_alarm();
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if ((time->tm_year < reference_year) || (time->tm_year > (reference_year + 63))) {
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return -2;
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}
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else {
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RTC->MODE2.Mode2Alarm[0].ALARM.reg = RTC_MODE2_ALARM_YEAR(time->tm_year - reference_year)
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| RTC_MODE2_ALARM_MONTH(time->tm_mon + 1)
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| RTC_MODE2_ALARM_DAY(time->tm_mday)
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| RTC_MODE2_ALARM_HOUR(time->tm_hour)
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| RTC_MODE2_ALARM_MINUTE(time->tm_min)
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| RTC_MODE2_ALARM_SECOND(time->tm_sec);
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RTC->MODE2.Mode2Alarm[0].MASK.reg = RTC_MODE2_MASK_SEL(6);
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while (RTC->MODE2.SYNCBUSY.bit.ALARM0);
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}
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/* Setup interrupt */
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NVIC_EnableIRQ(RTC_IRQn);
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/* Enable IRQ */
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rtc_callback.cb = cb;
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rtc_callback.arg = arg;
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RTC->MODE2.INTFLAG.bit.ALARM0 = 1;
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RTC->MODE2.INTENSET.bit.ALARM0 = 1;
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return 0;
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}
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int rtc_get_alarm(struct tm *time)
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{
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RTC_MODE2_ALARM_Type alarm;
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/* Read alarm register in one time */
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alarm.reg = RTC->MODE2.Mode2Alarm[0].ALARM.reg;
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time->tm_year = alarm.bit.YEAR + reference_year;
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if ((time->tm_year < reference_year) || (time->tm_year > (reference_year + 63))) {
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return -1;
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}
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time->tm_mon = alarm.bit.MONTH - 1;
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time->tm_mday = alarm.bit.DAY;
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time->tm_hour = alarm.bit.HOUR;
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time->tm_min = alarm.bit.MINUTE;
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time->tm_sec = alarm.bit.SECOND;
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return 0;
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}
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void rtc_clear_alarm(void)
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{
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/* disable interrupt */
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RTC->MODE2.INTENCLR.bit.ALARM0 = 1;
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rtc_callback.cb = NULL;
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rtc_callback.arg = NULL;
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}
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void rtc_poweron(void)
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{
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RTC->MODE2.CTRLA.bit.ENABLE = 1;
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while (RTC->MODE2.SYNCBUSY.bit.ENABLE);
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}
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void rtc_poweroff(void)
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{
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RTC->MODE2.CTRLA.bit.ENABLE = 0;
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while (RTC->MODE2.SYNCBUSY.bit.ENABLE);
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}
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void isr_rtc(void)
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{
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if (RTC->MODE2.INTFLAG.bit.ALARM0) {
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rtc_callback.cb(rtc_callback.arg);
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/* clear flag */
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RTC->MODE2.INTFLAG.bit.ALARM0 = 1;
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}
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if (RTC->MODE2.INTFLAG.bit.OVF) {
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/* clear flag */
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RTC->MODE2.INTFLAG.bit.OVF = 1;
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/* At 1Hz, RTC goes till 63 years (2^5, see 17.8.22 in datasheet)
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* Start RTC again with reference_year 64 years more (Be careful with alarm set) */
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reference_year += 64;
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}
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cortexm_isr_end();
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}
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#endif /* RTC_NUMOF */
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