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a73f3809cc
The CC26x2 and CC13x2 share the same register definitions, and both are treated equally in the TI's technical reference manual. [1] - To avoid confusions in the future I renamed it to `cc26x2_cc13x2`. - Documentation was updated. - The `cc1312-launchpad` board that uses the `cc13x2` MCU was updated. - The `cc1352-launchpad` board that uses the `cc13x2` MCU was updated. [1]: https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
238 lines
9.1 KiB
C
238 lines
9.1 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26x2_cc13x2_definitions
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* @{
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*
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* @file
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* @brief CC26x2, CC13x2 PRCM register definitions
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*/
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#ifndef CC26X2_CC13X2_PRCM_H
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#define CC26X2_CC13X2_PRCM_H
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#include <cc26xx_cc13xx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* DDI_0_OSC registers
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*/
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typedef struct {
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reg32_t CTL0; /**< control 0 */
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reg32_t CTL1; /**< control 1 */
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reg32_t RADCEXTCFG; /**< RADC external config */
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reg32_t AMPCOMPCTL; /**< amplitude compensation control */
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reg32_t AMPCOMPTH1; /**< amplitude compensation threshold 1 */
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reg32_t AMPCOMPTH2; /**< amplitude compensation threshold 2 */
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reg32_t ANABYPASSVAL1; /**< analog bypass values 1 */
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reg32_t ANABYPASSVAL2; /**< analog bypass values 2 */
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reg32_t ATESTCTL; /**< analog test control */
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reg32_t ADCDOUBLERNANOAMPCTL; /**< ADC doubler nanoamp control */
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reg32_t XOSCHFCTL; /**< XOSCHF control */
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reg32_t LFOSCCTL; /**< low frequency oscillator control */
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reg32_t RCOSCHFCTL; /**< RCOSCHF control */
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reg32_t RCOSCHMCTL; /**< RCOSCHM control */
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reg32_t STAT0; /**< status 0 */
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reg32_t STAT1; /**< status 1 */
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reg32_t STAT2; /**< status 2 */
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} ddi0_osc_regs_t;
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/**
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* @brief DDI_0_OSC register values
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* @{
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*/
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#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001
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#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL 0x0000000C
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#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL 0x00000180
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#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 /* enable clock loss detection */
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#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 /* bypass XOSC_LF and use digital input clock from AON foor xosx_lf (precuations in datasheet) */
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#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800
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#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000
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#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000
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#define DDI_0_OSC_CTL0_DCDC_SRC_SEL 0x01000000
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#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000
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#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION 0x0C000000
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#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
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#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000
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#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
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/** @} */
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/** @ingroup cpu_cc26x2_cc13x2_peripheral_memory_map
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* @{
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*/
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#define DDI0_OSC_BASE 0x400CA000 /**< DDI0_OSC base address */
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/*@}*/
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#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) /**< DDI_0_OSC register bank */
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/**
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* AON_PMCTL registers
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*/
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typedef struct {
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reg32_t __reserved1; /**< meh */
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reg32_t AUXSCECLK; /**< AUX SCE management */
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reg32_t RAMCFG; /**< RAM configuration */
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reg32_t __reserved2; /**< meh */
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reg32_t PWRCTL; /**< Power management control */
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reg32_t PWRSTAT; /**< Power status */
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reg32_t SHUTDOWN; /**< Shutdown control */
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reg32_t RECHARGECFG; /**< Recharge controller configuration */
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reg32_t RECHARGESTAT; /**< Recharge controller status */
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reg32_t OSCCFG; /**< Oscillator configuration */
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reg32_t RESETCTL; /**< Reset control */
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reg32_t SLEEPCTL; /**< Reset control */
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reg32_t __reserved3; /**< meh */
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reg32_t JTAGCFG; /**< JTAG configuration */
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reg32_t JTAGUSERCODE; /**< JTAG USERCODE */
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} aon_pmctl_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AON_PMCTL_BASE 0x40090000 /**< AON_PMCTL base address */
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/*@}*/
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#define AON_PMCTL ((aon_pmctl_regs_t *) (AON_PMCTL_BASE)) /**< AON_PMCTL register bank */
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/**
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* PRCM registers
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*/
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typedef struct {
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reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */
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reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */
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reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */
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reg32_t VDCTL; /**< MCU voltage domain control */
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reg32_t __reserved1[6]; /**< meh */
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reg32_t CLKLOADCTL; /**< clock load control */
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reg32_t RFCCLKG; /**< RFC clock gate */
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reg32_t VIMSCLKG; /**< VIMS clock gate */
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reg32_t __reserved2[2]; /**< meh */
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reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */
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reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */
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reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */
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reg32_t GPIOCLKGR; /**< GPIO clock gate for run mode */
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reg32_t GPIOCLKGS; /**< GPIO clock gate for sleep mode */
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reg32_t GPIOCLKGDS; /**< GPIO clock gate for deep sleep mode */
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reg32_t GPTCLKGR; /**< GPT clock gate for run mode */
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reg32_t GPTCLKGS; /**< GPT clock gate for sleep mode */
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reg32_t GPTCLKGDS; /**< GPT clock gate for deep sleep mode */
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reg32_t I2CCLKGR; /**< I2C clock gate for run mode */
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reg32_t I2CCLKGS; /**< I2C clock gate for sleep mode */
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reg32_t I2CCLKGDS; /**< I2C clock gate for deep sleep mode */
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reg32_t UARTCLKGR; /**< UART clock gate for run mode */
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reg32_t UARTCLKGS; /**< UART clock gate for sleep mode */
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reg32_t UARTCLKGDS; /**< UART clock gate for deep sleep mode */
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reg32_t SSICLKGR; /**< SSI clock gate for run mode */
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reg32_t SSICLKGS; /**< SSI clock gate for sleep mode */
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reg32_t SSICLKGDS; /**< SSI clock gate for deep sleep mode */
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reg32_t I2SCLKGR; /**< I2S clock gate for run mode */
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reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */
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reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */
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reg32_t __reserved3[9]; /**< meh */
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reg32_t SYSBUSCLKDIV; /**< System bus clock division factor */
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reg32_t CPUCLKDIV; /**< CPU clock division factor */
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reg32_t PERBUSCPUCLKDIV; /**< Peripheral bus division factor */
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reg32_t __reserved4; /**< meh */
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reg32_t PERDMACLKDIV; /**< DMA clock division factor */
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reg32_t I2SBCLKSEL; /**< I2S clock select */
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reg32_t GPTCLKDIV; /**< GPT scalar */
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reg32_t I2SCLKCTL; /**< I2S clock control */
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reg32_t I2SMCLKDIV; /**< MCLK division ratio */
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reg32_t I2SBCLKDIV; /**< BCLK division ratio */
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reg32_t I2SWCLKDIV; /**< WCLK division ratio */
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reg32_t __reserved5[4]; /**< meh */
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reg32_t RESETSECDMA; /**< Reset SEC and UDMA */
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reg32_t RESETGPIO; /**< Reset GPIO */
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reg32_t RESETGPT; /**< Reset GPTs */
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reg32_t RESETI2C; /**< Reset I2C */
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reg32_t RESETUART; /**< Reset UART */
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reg32_t RESETSSI; /**< Reset SSI */
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reg32_t RESETI2S; /**< Reset I2S */
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reg32_t __reserved6[8]; /**< meh */
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reg32_t PDCTL0; /**< power domain control */
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reg32_t PDCTL0RFC; /**< RFC power domain control */
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reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */
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reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */
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reg32_t __reserved7; /**< meh */
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reg32_t PDSTAT0; /**< power domain status */
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reg32_t PDSTAT0RFC; /**< RFC power domain status */
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reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */
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reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */
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reg32_t __reserved8[11]; /**< meh */
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reg32_t PDCTL1; /**< power domain control */
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reg32_t __reserved9; /**< power domain control */
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reg32_t PDCTL1CPU; /**< CPU power domain control */
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reg32_t PDCTL1RFC; /**< RFC power domain control */
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reg32_t PDCTL1VIMS; /**< VIMS power domain control */
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reg32_t __reserved10; /**< meh */
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reg32_t PDSTAT1; /**< power domain status */
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reg32_t PDSTAT1BUS; /**< BUS power domain status */
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reg32_t PDSTAT1RFC; /**< RFC power domain status */
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reg32_t PDSTAT1CPU; /**< CPU power domain status */
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reg32_t PDSTAT1VIMS; /**< VIMS power domain status */
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reg32_t __reserved11[9]; /**< meh */
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reg32_t RFCBITS; /**< Control to RFC */
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reg32_t RFCMODESEL; /**< selected RFC mode */
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reg32_t RFCMODEHWOPT; /**< allowed RFC modes */
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reg32_t __reserved12[2]; /**< meh */
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reg32_t PWRPROFSTAT; /**< power profiler register */
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reg32_t __reserved13[14]; /**< meh */
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reg32_t MCUSRAMCFG; /**< MCU SRAM configuration */
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reg32_t __reserved14; /**< meh */
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reg32_t RAMRETEN; /**< memory retention control */
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reg32_t __reserved15[27]; /**< meh */
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reg32_t OSCIMSC; /**< oscillator interrupt mask */
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reg32_t OSCRIS; /**< oscillator raw interrupt status */
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reg32_t OSCICR; /**< oscillator raw interrupt clear */
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} prcm_regs_t;
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/**
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* @brief PRCM register values
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* @{
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*/
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#define CLKLOADCTL_LOAD 0x1
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#define CLKLOADCTL_LOADDONE 0x2
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#define PDCTL0_RFC_ON 0x1
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#define PDCTL0_SERIAL_ON 0x2
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#define PDCTL0_PERIPH_ON 0x4
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#define PDSTAT0_RFC_ON 0x1
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#define PDSTAT0_SERIAL_ON 0x2
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#define PDSTAT0_PERIPH_ON 0x4
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#define PDCTL1_CPU_ON 0x2
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#define PDCTL1_RFC_ON 0x4
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#define PDCTL1_VIMS_ON 0x8
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#define PDSTAT1_CPU_ON 0x2
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#define PDSTAT1_RFC_ON 0x4
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#define PDSTAT1_VIMS_ON 0x8
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define PRCM_BASE 0x40082000 /**< PRCM base address */
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/*@}*/
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#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC26X2_CC13X2_PRCM_H */
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/*@}*/
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