mirror of
https://github.com/RIOT-OS/RIOT.git
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302 lines
10 KiB
C
302 lines
10 KiB
C
/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_frdm-kw41z
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the FRDM-KW41Z
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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static const clock_config_t clock_config = {
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/*
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* This configuration results in the system running with the internal clock
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* with the following clock frequencies:
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* Core: 48 MHz
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* Bus: 24 MHz
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* Flash: 24 MHz
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*/
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1),
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/* unsure if this RTC load cap configuration is correct, but it matches the
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* settings used by the example code in the NXP provided SDK */
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.rtc_clc = 0,
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/* Use the 32 kHz oscillator as ERCLK32K. Note that the values here have a
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* different mapping for the KW41Z than the values used in the Kinetis K series */
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.osc32ksel = SIM_SOPT1_OSC32KSEL(0),
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.clock_flags =
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KINETIS_CLOCK_OSC0_EN | /* Enable RSIM oscillator */
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KINETIS_CLOCK_RTCOSC_EN |
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KINETIS_CLOCK_USE_FAST_IRC |
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KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
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KINETIS_CLOCK_MCGIRCLK_STOP_EN |
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0,
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/* Using FEI mode by default, the external crystal settings below are only
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* used if mode is changed to an external mode (PEE, FBE, or FEE) */
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.default_mode = KINETIS_MCG_MODE_FEI,
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/* The crystal connected to RSIM OSC is 32 MHz */
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.erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH,
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.osc_clc = 0, /* no load cap configuration */
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.oscsel = MCG_C7_OSCSEL(0), /* Use RSIM for external clock */
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.fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
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.fll_frdiv = MCG_C1_FRDIV(0b101), /* Divide by 1024 */
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.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FEI FLL freq = 48 MHz */
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.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280, /* FEE FLL freq = 40 MHz */
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};
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/* Radio xtal frequency, either 32 MHz or 26 MHz */
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#define CLOCK_RADIOXTAL (32000000ul)
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/* CPU core clock, the MCG clock output frequency */
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#define CLOCK_CORECLOCK (48000000ul)
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#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
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#define CLOCK_MCGIRCLK (4000000ul)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define PIT_NUMOF (1U)
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#define PIT_CONFIG { \
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{ \
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.prescaler_ch = 0, \
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.count_ch = 1, \
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}, \
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}
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#define LPTMR_NUMOF (1U)
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#define LPTMR_CONFIG { \
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{ \
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.dev = LPTMR0, \
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.irqn = LPTMR0_IRQn, \
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} \
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}
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#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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#define LPTMR_ISR_0 isr_lptmr0
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = LPUART0,
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.freq = CLOCK_MCGIRCLK,
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.pin_rx = GPIO_PIN(PORT_C, 6),
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.pin_tx = GPIO_PIN(PORT_C, 7),
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.pcr_rx = PORT_PCR_MUX(4),
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.pcr_tx = PORT_PCR_MUX(4),
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.irqn = LPUART0_IRQn,
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.scgc_addr = &SIM->SCGC5,
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.scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
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.mode = UART_MODE_8N1,
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.type = KINETIS_LPUART,
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},
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};
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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#define LPUART_0_ISR isr_lpuart0
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/* Use MCGIRCLK (internal reference 4 MHz clock) */
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#define LPUART_0_SRC 3
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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/* dev, pin, channel */
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[ 0] = { ADC0, GPIO_UNDEF, 26 }, /* internal: temperature sensor */
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/* Note: the band gap buffer uses a bit of current and is turned off by default,
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* Set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading or the input will be floating */
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[ 1] = { ADC0, GPIO_UNDEF, 27 }, /* internal: band gap */
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[ 2] = { ADC0, GPIO_UNDEF, 29 }, /* internal: V_REFH */
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[ 3] = { ADC0, GPIO_UNDEF, 30 }, /* internal: V_REFL */
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[ 4] = { ADC0, GPIO_UNDEF, 23 }, /* internal: DCDC divided battery level */
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[ 5] = { ADC0, GPIO_UNDEF, 0 | ADC_SC1_DIFF_MASK }, /* ADC0_DP-ADC0_DM differential reading */
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[ 6] = { ADC0, GPIO_PIN(PORT_B, 3), 2 }, /* ADC0_SE2 */
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[ 7] = { ADC0, GPIO_PIN(PORT_B, 2), 3 }, /* ADC0_SE3 */
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};
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#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
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/*
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* KW41Z ADC reference settings:
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* 0: VREFH external pin or VREF_OUT 1.2 V signal (if VREF module is enabled)
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* 1: VDDA (analog supply input voltage)
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* 2-3: reserved
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*
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* VREF_OUT and VREFH shares the pin on KW41Z and is only connected to a 100 nF
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* capacitor on the FRDM-KW41Z board. So use VDDA by default on this board
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* unless the application enables the VREF module.
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*/
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#define ADC_REF_SETTING 1
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/** @} */
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/**
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* @name SPI configuration
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*
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* Clock configuration values based on the configured 16Mhz module clock.
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*
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* Auto-generated by:
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* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
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*
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* @{
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*/
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static const uint32_t spi_clk_config[] = {
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) | /* -> 100000Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(4)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) | /* -> 400000Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(2)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | /* -> 1000000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(3)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(0)
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)
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0,
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.pin_miso = GPIO_PIN(PORT_C, 18),
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.pin_mosi = GPIO_PIN(PORT_C, 17),
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.pin_clk = GPIO_PIN(PORT_C, 16),
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.pin_cs = {
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GPIO_PIN(PORT_C, 19),
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI0_MASK
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},
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{
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.dev = SPI1,
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.pin_miso = GPIO_PIN(PORT_A, 17),
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.pin_mosi = GPIO_PIN(PORT_A, 16),
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.pin_clk = GPIO_PIN(PORT_A, 18),
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.pin_cs = {
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GPIO_PIN(PORT_A, 19),
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI1_MASK
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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/* This CPU has I2C0 clocked by the bus clock and I2C1 clocked by the system
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* clock. This causes trouble with the current implementation in kinetis
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* which only supports one set of frequency dividers at a time */
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/* The current configuration sets the dividers so that the I2C0 bus will run at
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* half the requested speed, to avoid exceeding the requested speed on I2C1 with
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* the same configuration */
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#define I2C_NUMOF (2U)
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#define I2C_0_EN 1
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/* Disabled while waiting for a rewritten i2c driver which supports different
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* clock sources for each i2c module */
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#define I2C_1_EN 1
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/* Low (10 kHz): MUL = 2, SCL divider = 1792, total: 3584 */
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#define KINETIS_I2C_F_ICR_LOW (0x3A)
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#define KINETIS_I2C_F_MULT_LOW (1)
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/* Normal (100 kHz): MUL = 1, SCL divider = 320, total: 320 */
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#define KINETIS_I2C_F_ICR_NORMAL (0x25)
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#define KINETIS_I2C_F_MULT_NORMAL (0)
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/* Fast (400 kHz): MUL = 1, SCL divider = 80, total: 80 */
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#define KINETIS_I2C_F_ICR_FAST (0x14)
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#define KINETIS_I2C_F_MULT_FAST (0)
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/* Fast plus (1000 kHz): MUL = 1, SCL divider = 32, total: 32 */
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#define KINETIS_I2C_F_ICR_FAST_PLUS (0x09)
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#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C0
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#define I2C_0_CLKEN() (bit_set32(&SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT))
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#define I2C_0_CLKDIS() (bit_clear32(&SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT))
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#define I2C_0_IRQ I2C0_IRQn
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#define I2C_0_IRQ_HANDLER isr_i2c0
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/* I2C 0 pin configuration */
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#define I2C_0_PORT PORTB
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#define I2C_0_PORT_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
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#define I2C_0_PIN_AF 3
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#define I2C_0_SDA_PIN 1
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#define I2C_0_SCL_PIN 0
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#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF))
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/* I2C 1 device configuration */
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#define I2C_1_DEV I2C1
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#define I2C_1_CLKEN() (bit_set32(&SIM->SCGC4, SIM_SCGC4_I2C1_SHIFT))
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#define I2C_1_CLKDIS() (bit_clear32(&SIM->SCGC4, SIM_SCGC4_I2C1_SHIFT))
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#define I2C_1_IRQ I2C1_IRQn
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#define I2C_1_IRQ_HANDLER isr_i2c1
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/* I2C 1 pin configuration */
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#define I2C_1_PORT PORTC
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#define I2C_1_PORT_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
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#define I2C_1_PIN_AF 3
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#define I2C_1_SDA_PIN 3
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#define I2C_1_SCL_PIN 2
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#define I2C_1_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF))
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/** @} */
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define KINETIS_TRNG TRNG
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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