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159 lines
8.6 KiB
C
159 lines
8.6 KiB
C
/******************************************************************************
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* Filename: hw_memmap_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_MEMMAP_H__
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#define __HW_MEMMAP_H__
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//*****************************************************************************
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//
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// The following are defines for the base address of the memories and
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// peripherals on the CPU_MMAP interface
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//
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//*****************************************************************************
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#define FLASHMEM_BASE 0x00000000 // FLASHMEM
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#define BROM_BASE 0x10000000 // BROM
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#define GPRAM_BASE 0x11000000 // GPRAM
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#define SRAM_BASE 0x20000000 // SRAM
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#define RFC_RAM_BASE 0x21000000 // RFC_RAM
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#define SSI0_BASE 0x40000000 // SSI
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//#define UART0_BASE 0x40001000 // UART
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#define I2C0_BASE 0x40002000 // I2C
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#define SSI1_BASE 0x40008000 // SSI
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//#define GPT0_BASE 0x40010000 // GPT
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//#define GPT1_BASE 0x40011000 // GPT
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//#define GPT2_BASE 0x40012000 // GPT
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//#define GPT3_BASE 0x40013000 // GPT
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#define UDMA0_BASE 0x40020000 // UDMA
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#define I2S0_BASE 0x40021000 // I2S
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//#define GPIO_BASE 0x40022000 // GPIO
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#define CRYPTO_BASE 0x40024000 // CRYPTO
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#define TRNG_BASE 0x40028000 // TRNG
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//#define FLASH_BASE 0x40030000 // FLASH
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//#define VIMS_BASE 0x40034000 // VIMS
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//#define RFC_PWR_BASE 0x40040000 // RFC_PWR
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//#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL
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#define RFC_RAT_BASE 0x40043000 // RFC_RAT
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#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA
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#define WDT_BASE 0x40080000 // WDT
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#define IOC_BASE 0x40081000 // IOC
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//#define PRCM_BASE 0x40082000 // PRCM
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#define EVENT_BASE 0x40083000 // EVENT
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#define SMPH_BASE 0x40084000 // SMPH
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#define ADI2_BASE 0x40086000 // ADI
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#define ADI3_BASE 0x40086200 // ADI
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#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL
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#define AON_WUC_BASE 0x40091000 // AON_WUC
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//#define AON_RTC_BASE 0x40092000 // AON_RTC
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#define AON_EVENT_BASE 0x40093000 // AON_EVENT
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//#define AON_IOC_BASE 0x40094000 // AON_IOC
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#define AON_BATMON_BASE 0x40095000 // AON_BATMON
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#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO
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#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO
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#define AUX_TDC_BASE 0x400C4000 // AUX_TDC
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#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL
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#define AUX_WUC_BASE 0x400C6000 // AUX_WUC
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#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER
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#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH
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#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF
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#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI
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#define AUX_ADI4_BASE 0x400CB000 // ADI
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#define AUX_RAM_BASE 0x400E0000 // AUX_RAM
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#define AUX_SCE_BASE 0x400E1000 // AUX_SCE
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#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP
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#define FCFG1_BASE 0x50001000 // FCFG1
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#define FCFG2_BASE 0x50002000 // FCFG2
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#ifndef CCFG_BASE
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//#define CCFG_BASE 0x50003000 // CCFG
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#endif
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#define CCFG_BASE_DEFAULT 0x50003000 // CCFG
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#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base
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#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base
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#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base
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#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base
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#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base
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#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base
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#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base
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#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base
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#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base
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#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base
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#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base
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#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base
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#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base
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#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base
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#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base
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#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base
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#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base
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#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base
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#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base
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#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base
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#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base
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#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base
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#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base
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#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base
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#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base
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#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base
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#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base
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#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base
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#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base
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#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base
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#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base
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#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base
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#define AUX_AIODIO0_NONBUF_BASE \
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0x600C1000 // AUX_AIODIO CPU nonbuf base
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#define AUX_AIODIO1_NONBUF_BASE \
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0x600C2000 // AUX_AIODIO CPU nonbuf base
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#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base
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#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base
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#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base
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#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base
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#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base
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#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base
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#define AUX_DDI0_OSC_NONBUF_BASE \
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0x600CA000 // DDI CPU nonbuf base
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#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base
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#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base
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#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base
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#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base
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#define CPU_ITM_BASE 0xE0000000 // CPU_ITM
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#define CPU_DWT_BASE 0xE0001000 // CPU_DWT
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#define CPU_FPB_BASE 0xE0002000 // CPU_FPB
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#define CPU_SCS_BASE 0xE000E000 // CPU_SCS
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#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU
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#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP
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#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE
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#endif // __HW_MEMMAP__
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