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424 lines
17 KiB
C
424 lines
17 KiB
C
/******************************************************************************
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* Filename: sys_ctrl.c
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* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018)
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* Revision: 52220
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*
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* Description: Driver for the System Control.
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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// Hardware headers
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#include "../inc/hw_types.h"
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#include "../inc/hw_ccfg.h"
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#include "../inc/hw_adi.h"
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// Driverlib headers
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#include "aon_batmon.h"
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#include "setup_rom.h"
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#include "sys_ctrl.h"
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//*****************************************************************************
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//
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// Handle support for DriverLib in ROM:
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// This section will undo prototype renaming made in the header file
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//
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//*****************************************************************************
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#if !defined(DOXYGEN)
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#undef SysCtrlSetRechargeBeforePowerDown
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#define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown
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#undef SysCtrlAdjustRechargeAfterPowerDown
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#define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown
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#undef SysCtrl_DCDC_VoltageConditionalControl
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#define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl
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#undef SysCtrlResetSourceGet
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#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet
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#endif
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//*****************************************************************************
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//
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// Recharge calculator defines and globals
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//
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//*****************************************************************************
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#define PD_STATE_CACHE_RET 1
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#define PD_STATE_RFMEM_RET 2
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#define PD_STATE_XOSC_LPM 4
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#define PD_STATE_EXT_REG_MODE 8
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typedef struct {
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uint32_t pdTime ;
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uint16_t pdRechargePeriod ;
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uint8_t pdState ;
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int8_t pdTemp ;
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} PowerQualGlobals_t;
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static PowerQualGlobals_t powerQualGlobals;
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//*****************************************************************************
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//
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// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode )
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//
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//*****************************************************************************
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void
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SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode )
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{
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int32_t curTemp ;
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int32_t shiftedTemp ;
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int32_t deltaVddrSleepTrim ;
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int32_t vddrTrimSleep ;
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int32_t vddrTrimActve ;
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int32_t diffVddrActiveSleep ;
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uint32_t ccfg_ModeConfReg ;
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uint32_t curState ;
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uint32_t prcmRamRetention ;
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uint32_t di ;
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uint32_t dii ;
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uint32_t ti ;
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uint32_t cd ;
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uint32_t cl ;
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uint32_t load ;
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uint32_t k ;
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uint32_t vddrCap ;
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uint32_t newRechargePeriod ;
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uint32_t perE ;
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uint32_t perM ;
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const uint32_t * pLookupTable ;
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// If external regulator mode we shall:
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// - Disable adaptive recharge (bit[31]=0) in AON_WUC_O_RECHARGECFG
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// - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD)
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// - Make sure you get a recalculation if leaving external regulator mode by setting powerQualGlobals.pdState accordingly
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if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) {
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powerQualGlobals.pdState = PD_STATE_EXT_REG_MODE;
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HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = 0x00A4FDFD;
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return;
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}
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//--- Spec. point 1 ---
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curTemp = AONBatMonTemperatureGetDegC();
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curState = 0;
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// read the MODE_CONF register in CCFG
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ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
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// Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended)
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deltaVddrSleepTrim = ((((int32_t) ccfg_ModeConfReg )
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<< ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))
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>> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1;
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// Do temperature compensation if enabled
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if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) {
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int32_t tcDelta = ( 62 - curTemp ) >> 3;
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if ( tcDelta > 8 ) tcDelta = 8;
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if ( tcDelta > deltaVddrSleepTrim ) deltaVddrSleepTrim = tcDelta;
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}
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{
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vddrTrimSleep = SetupSignExtendVddrTrimValue((
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HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) &
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FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >>
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FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ;
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vddrTrimActve = SetupSignExtendVddrTrimValue((
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HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ) &
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FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >>
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FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ;
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}
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vddrTrimSleep += deltaVddrSleepTrim;
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if ( vddrTrimSleep > 21 ) vddrTrimSleep = 21;
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if ( vddrTrimSleep < -10 ) vddrTrimSleep = -10;
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// Write adjusted value using MASKED write (MASK8)
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HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) |
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(( vddrTrimSleep << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M ));
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prcmRamRetention = HWREG( PRCM_BASE + PRCM_O_RAMRETEN );
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if ( prcmRamRetention & PRCM_RAMRETEN_VIMS_M ) {
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curState |= PD_STATE_CACHE_RET;
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}
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if ( prcmRamRetention & PRCM_RAMRETEN_RFC ) {
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curState |= PD_STATE_RFMEM_RET;
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}
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if ( xoscPowerMode != XOSC_IN_HIGH_POWER_MODE ) {
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curState |= PD_STATE_XOSC_LPM;
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}
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//--- Spec. point 2 ---
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if ((( curTemp - powerQualGlobals.pdTemp ) >= 5 ) || ( curState != powerQualGlobals.pdState )) {
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//--- Spec. point 3 ---
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shiftedTemp = curTemp - 15;
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//--- Spec point 4 ---
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//4. Check for external VDDR load option (may not be supported): ext_load = (VDDR_EXT_LOAD=0 in CCFG)
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// Currently not implementing external load handling
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// if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) {
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// }
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pLookupTable = (uint32_t *)( FCFG1_BASE + FCFG1_O_PWD_CURR_20C );
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//--- Spec point 5 ---
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di = 0;
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ti = 0;
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if ( shiftedTemp >= 0 ) {
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//--- Spec point 5.a ---
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shiftedTemp += ( shiftedTemp << 4 );
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//--- Spec point 5.b ---
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ti = ( shiftedTemp >> 8 );
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if ( ti > 7 ) {
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ti = 7;
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}
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dii = ti;
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if ( dii > 6 ) {
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dii = 6;
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}
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//--- Spec point 5.c ---
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cd = pLookupTable[ dii + 1 ] - pLookupTable[ dii ];
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//--- Spec point 5.d ---
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di = cd & 0xFF;
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//--- Spec point 5.e ---
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if ( curState & PD_STATE_XOSC_LPM ) {
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di += (( cd >> 8 ) & 0xFF );
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}
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if ( curState & PD_STATE_RFMEM_RET ) {
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di += (( cd >> 16 ) & 0xFF );
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}
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if ( curState & PD_STATE_CACHE_RET ) {
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di += (( cd >> 24 ) & 0xFF );
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}
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//--- Spec point 5.f ---
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// Currently not implementing external load handling
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}
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//--- Spec. point 6 ---
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cl = pLookupTable[ ti ];
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//--- Spec. point 7 ---
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load = cl & 0xFF;
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//--- Spec. point 8 ---
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if ( curState & PD_STATE_XOSC_LPM ) {
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load += (( cl >> 8 ) & 0xFF );
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}
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if ( curState & PD_STATE_RFMEM_RET ) {
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load += (( cl >> 16 ) & 0xFF );
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}
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if ( curState & PD_STATE_CACHE_RET ) {
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load += (( cl >> 24 ) & 0xFF );
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}
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//--- Spec. point 9 ---
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load += ((( di * ( shiftedTemp - ( ti << 8 ))) + 128 ) >> 8 );
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// Currently not implementing external load handling
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// if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) {
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//--- Spec. point 10 ---
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// } else {
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//--- Spec. point 11 ---
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diffVddrActiveSleep = ( vddrTrimActve - vddrTrimSleep );
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if ( diffVddrActiveSleep < 1 ) diffVddrActiveSleep = 1;
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k = ( diffVddrActiveSleep * 52 );
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// }
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//--- Spec. point 12 ---
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vddrCap = ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_CAP_M ) >> CCFG_MODE_CONF_VDDR_CAP_S;
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newRechargePeriod = ( vddrCap * k ) / load;
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if ( newRechargePeriod > 0xFFFF ) {
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newRechargePeriod = 0xFFFF;
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}
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powerQualGlobals.pdRechargePeriod = newRechargePeriod;
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//--- Spec. point 13 ---
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if ( curTemp > 127 ) curTemp = 127;
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if ( curTemp < -128 ) curTemp = -128;
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powerQualGlobals.pdTemp = curTemp;
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powerQualGlobals.pdState = curState;
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}
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powerQualGlobals.pdTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );
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// Calculate PER_E and PER_M (based on powerQualGlobals.pdRechargePeriod)
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// Round downwards but make sure PER_E=0 and PER_M=1 is the minimum possible setting.
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// (assuming that powerQualGlobals.pdRechargePeriod always are <= 0xFFFF)
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perE = 0;
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perM = powerQualGlobals.pdRechargePeriod;
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if ( perM < 31 ) {
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perM = 31;
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powerQualGlobals.pdRechargePeriod = 31;
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}
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while ( perM > 511 ) {
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perM >>= 1;
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perE += 1;
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}
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perM = ( perM - 15 ) >> 4;
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HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) =
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( 0x80A4E700 ) |
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( perM << AON_WUC_RECHARGECFG_PER_M_S ) |
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( perE << AON_WUC_RECHARGECFG_PER_E_S ) ;
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HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) = 0;
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}
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//*****************************************************************************
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//
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// SysCtrlAdjustRechargeAfterPowerDown()
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//
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//*****************************************************************************
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void
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SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin )
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{
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int32_t curTemp ;
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uint32_t longestRechargePeriod ;
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uint32_t deltaTime ;
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uint32_t newRechargePeriod ;
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//--- Spec. point 2 ---
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longestRechargePeriod = ( HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) &
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AON_WUC_RECHARGESTAT_MAX_USED_PER_M ) >>
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AON_WUC_RECHARGESTAT_MAX_USED_PER_S ;
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if ( longestRechargePeriod != 0 ) {
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//--- Spec. changed (originally point 1) ---
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curTemp = AONBatMonTemperatureGetDegC();
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if ( curTemp < powerQualGlobals.pdTemp ) {
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if ( curTemp < -128 ) {
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curTemp = -128;
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}
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powerQualGlobals.pdTemp = curTemp;
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}
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// Add some margin between the longest previous recharge period and the
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// next initial recharge period. Since it is a fixed margin, it will have a
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// higher impact as a fraction of the converged recharge period at higher temperatures
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// where it is needed more due to higher leakage.
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if (longestRechargePeriod > vddrRechargeMargin) {
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longestRechargePeriod -= vddrRechargeMargin;
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}
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else {
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longestRechargePeriod = 1;
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}
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//--- Spec. point 4 ---
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if ( longestRechargePeriod < powerQualGlobals.pdRechargePeriod ) {
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powerQualGlobals.pdRechargePeriod = longestRechargePeriod;
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} else {
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//--- Spec. point 5 ---
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deltaTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ) - powerQualGlobals.pdTime + 2;
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if ( deltaTime > 31 ) {
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deltaTime = 31;
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}
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newRechargePeriod = powerQualGlobals.pdRechargePeriod + (( longestRechargePeriod - powerQualGlobals.pdRechargePeriod ) >> (deltaTime>>1));
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if ( newRechargePeriod > 0xFFFF ) {
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newRechargePeriod = 0xFFFF;
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}
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powerQualGlobals.pdRechargePeriod = newRechargePeriod;
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}
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}
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}
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//*****************************************************************************
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//
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// SysCtrl_DCDC_VoltageConditionalControl()
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//
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//*****************************************************************************
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void
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SysCtrl_DCDC_VoltageConditionalControl( void )
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{
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uint32_t batThreshold ; // Fractional format with 8 fractional bits.
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uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits.
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uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register.
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uint32_t aonSysctlPwrctl ; // Reflect whats read/written to the AON_SYSCTL_O_PWRCTL register.
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// We could potentially call this function before any battery voltage measurement
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// is made/available. In that case we must make sure that we do not turn off the DCDC.
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// This can be done by doing nothing as long as the battery voltage is 0 (Since the
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// reset value of the battery voltage register is 0).
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aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT );
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if ( aonBatmonBat != 0 ) {
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// Check if Voltage Conditional Control is enabled
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// It is enabled if all the following are true:
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// - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero).
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// - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 )
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// - Not in external regulator mode ( EXT_REG_MODE == 0 )
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ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
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if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) ||
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(( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) &&
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(( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) == 0 ) &&
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(( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) )
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{
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aonSysctlPwrctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL );
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batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
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CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >>
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CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 );
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if ( aonSysctlPwrctl & ( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M )) {
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// DCDC is ON, check if it should be switched off
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if ( aonBatmonBat < batThreshold ) {
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aonSysctlPwrctl &= ~( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M );
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HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl;
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}
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} else {
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// DCDC is OFF, check if it should be switched on
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if ( aonBatmonBat > batThreshold ) {
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if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_EN_M ;
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if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ;
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HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl;
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}
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}
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}
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}
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}
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//*****************************************************************************
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//
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// SysCtrlResetSourceGet()
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//
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//*****************************************************************************
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uint32_t
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SysCtrlResetSourceGet( void )
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{
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uint32_t aonSysctlResetCtl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL );
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if ( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_WU_FROM_SD_M ) {
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return ( RSTSRC_WAKEUP_FROM_SHUTDOWN );
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} else {
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return (( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> AON_SYSCTL_RESETCTL_RESET_SRC_S ) ;
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}
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}
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