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d3e0b78f7c
In the `pwm_set` function, the switch-on and switch-off times for PWM channels were only determined for the following phase, but not for the current phase. This could result in a missing duty cycle when calling the function `pwm_set` if the switch-on time of the current phase was not yet reached or to an extended duty cycle if the switch-off time of the current phase had not yet been reached.
251 lines
6.1 KiB
C
251 lines
6.1 KiB
C
/*
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* Copyright (C) 2018 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp8266
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* @ingroup drivers_periph_pwm
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* @{
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*
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* @file
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* @brief Low-level PWM driver implementation
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @}
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*/
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#include "cpu.h"
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#include "log.h"
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#include "irq_arch.h"
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#include "periph/pwm.h"
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#include "periph/gpio.h"
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#include "common.h"
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#include "esp/iomux_regs.h"
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#include "esp/timer_regs.h"
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#include "gpio_common.h"
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#include "sdk/ets.h"
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#if defined(PWM_NUMOF) && PWM_NUMOF > 0
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#define TIMER_FRC1_CLKDIV_16 BIT(2)
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#define TIMER_FRC1_CLKDIV_256 BIT(3)
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#define ETS_FRC1_INT_ENABLE ETS_FRC1_INTR_ENABLE
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#define ETS_FRC1_INT_DISABLE ETS_FRC1_INTR_DISABLE
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#define ETS_FRC1_INT_ATTACH ETS_FRC_TIMER1_INTR_ATTACH
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#define ETS_FRC1_NMI_ATTACH ETS_FRC_TIMER1_NMI_INTR_ATTACH
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typedef struct
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{
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uint16_t duty;
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uint32_t next_on;
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uint32_t next_off;
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gpio_t gpio;
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} _pwm_chn_t;
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typedef struct
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{
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pwm_mode_t mode;
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uint16_t res;
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uint32_t load;
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uint32_t cycles;
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uint8_t chn_num;
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_pwm_chn_t chn[PWM_CHANNEL_NUM_MAX];
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} _pwm_dev_t;
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static _pwm_dev_t _pwm_dev;
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static const uint32_t _pwm_channel_gpios[] = PWM0_CHANNEL_GPIOS;
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static void _pwm_timer_handler (void* arg)
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{
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irq_isr_enter ();
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_pwm_dev.cycles++;
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for (int i = 0; i < _pwm_dev.chn_num; i++) {
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if (_pwm_dev.chn[i].duty != 0 &&
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_pwm_dev.chn[i].next_on == _pwm_dev.cycles) {
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gpio_set (_pwm_dev.chn[i].gpio);
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_pwm_dev.chn[i].next_on += _pwm_dev.res;
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}
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else if (_pwm_dev.chn[i].duty < _pwm_dev.res &&
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_pwm_dev.chn[i].next_off == _pwm_dev.cycles) {
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gpio_clear (_pwm_dev.chn[i].gpio);
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_pwm_dev.chn[i].next_off += _pwm_dev.res;
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}
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}
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irq_isr_exit ();
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}
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static void _pwm_start(void)
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{
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/* enable the timer and the interrupt and load the counter */
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TIMER_FRC1.CTRL = TIMER_FRC1_CLKDIV_16 | TIMER_CTRL_RELOAD | TIMER_CTRL_RUN;
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TM1_EDGE_INT_ENABLE();
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ETS_FRC1_INT_ENABLE();
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TIMER_FRC1.LOAD = _pwm_dev.load;
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_pwm_dev.cycles = 0;
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/* set the duty for all channels to start them */
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for (int i = 0; i < _pwm_dev.chn_num; i++) {
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pwm_set(PWM_DEV(0), i, _pwm_dev.chn[i].duty);
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}
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}
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static void _pwm_stop(void)
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{
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/* disable the interrupt and the timer */
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ETS_FRC1_INT_DISABLE();
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TM1_EDGE_INT_DISABLE();
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TIMER_FRC1.CTRL &= ~TIMER_CTRL_RUN;
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}
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#define PWM_MAX_CPS 100000UL /* maximum cycles per second */
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uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
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{
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DEBUG ("%s pwm=%u mode=%u freq=%u, res=%u\n", __func__, pwm, mode, freq, res);
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uint8_t _pwm_channel_gpio_num = sizeof(_pwm_channel_gpios) >> 2;
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CHECK_PARAM_RET (pwm < PWM_NUMOF, 0);
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CHECK_PARAM_RET (freq > 0, 0);
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CHECK_PARAM_RET (_pwm_channel_gpio_num <= PWM_CHANNEL_NUM_MAX, 0);
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/* maximum number of cycles per second (freq*res) should not be greater than */
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/* 100.000 (period of 10 us), reduce freq if neccessary and keep resolution */
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if (res * freq > PWM_MAX_CPS) {
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freq = PWM_MAX_CPS / res;
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}
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_pwm_dev.load = 5e6 / freq / res; /* load value for FRC1 at TIMER_FRC1_CLKDIV_16 */
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_pwm_dev.res = res;
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_pwm_dev.chn_num = 0;
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_pwm_dev.cycles = 0;
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_pwm_dev.mode = mode;
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for (int i = 0; i < _pwm_channel_gpio_num; i++) {
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if (_gpio_pin_usage[_pwm_channel_gpios[i]] != _GPIO) {
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LOG_ERROR("GPIO%d is used for something else and cannot be used as PWM output\n", i);
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return 0;
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}
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if (gpio_init(_pwm_channel_gpios[i], GPIO_OUT) < 0) {
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return 0;
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}
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gpio_clear (_pwm_channel_gpios[i]);
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_pwm_dev.chn[_pwm_dev.chn_num].duty = 0;
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_pwm_dev.chn[_pwm_dev.chn_num].next_on = 0;
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_pwm_dev.chn[_pwm_dev.chn_num].next_off = 0;
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_pwm_dev.chn[_pwm_dev.chn_num].gpio = _pwm_channel_gpios[i];
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_pwm_dev.chn_num++;
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}
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TIMER_FRC1.CTRL = TIMER_FRC1_CLKDIV_16 | TIMER_CTRL_RELOAD | TIMER_CTRL_RUN;
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ETS_FRC1_INT_ATTACH(_pwm_timer_handler,0);
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TM1_EDGE_INT_ENABLE();
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ETS_FRC1_INT_ENABLE();
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TIMER_FRC1.LOAD = _pwm_dev.load;
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return freq;
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}
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uint8_t pwm_channels(pwm_t pwm)
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{
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CHECK_PARAM_RET (pwm < PWM_NUMOF, 0);
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return _pwm_dev.chn_num;
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}
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void pwm_set(pwm_t pwm, uint8_t channel, uint16_t value)
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{
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DEBUG("%s pwm=%u channel=%u value=%u\n", __func__, pwm, channel, value);
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CHECK_PARAM (pwm < PWM_NUMOF);
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CHECK_PARAM (channel < _pwm_dev.chn_num);
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CHECK_PARAM (value <= _pwm_dev.res);
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uint32_t state = irq_disable();
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uint32_t phase = _pwm_dev.cycles - _pwm_dev.cycles % _pwm_dev.res;
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uint32_t next_on = phase;
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uint32_t next_off;
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switch (_pwm_dev.mode) {
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case PWM_LEFT:
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next_on = phase;
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break;
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case PWM_RIGHT:
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next_on = phase + _pwm_dev.res - value;
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break;
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case PWM_CENTER:
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next_on = phase + (_pwm_dev.res - value) / 2;
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break;
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}
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next_off = next_on + value;
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if (_pwm_dev.cycles >= next_on) {
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next_on += _pwm_dev.res;
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}
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if (_pwm_dev.cycles >= next_off) {
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next_off += _pwm_dev.res;
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}
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_pwm_dev.chn[channel].next_on = next_on;
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_pwm_dev.chn[channel].next_off = next_off;
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_pwm_dev.chn[channel].duty = value;
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irq_restore(state);
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}
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void pwm_poweron(pwm_t pwm)
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{
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CHECK_PARAM (pwm < PWM_NUMOF);
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_pwm_start();
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}
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void pwm_poweroff(pwm_t pwm)
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{
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CHECK_PARAM (pwm < PWM_NUMOF);
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_pwm_stop ();
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}
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void pwm_print_config(void)
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{
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LOG_INFO("\tPWM_DEV(0): channels=[ ");
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for (unsigned i = 0; i < sizeof(_pwm_channel_gpios) >> 2; i++) {
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LOG_INFO("%d ", _pwm_channel_gpios[i]);
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}
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LOG_INFO("]\n");
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}
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#else /* defined(PWM_NUMOF) && PWM_NUMOF > 0 */
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void pwm_print_config(void)
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{
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LOG_INFO("\tPWM: no devices\n");
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}
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#endif /* defined(PWM_NUMOF) && PWM_NUMOF > 0 */
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