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114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_cortexm_common ARM Cortex-M common
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* @ingroup cpu
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* @brief Common implementations and headers for Cortex-M family based
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* micro-controllers
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* @{
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*
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* @file
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* @brief Basic definitions for the Cortex-M common module
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*
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* When ever you want to do something hardware related, that is accessing MCUs
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* registers, just include this file. It will then make sure that the MCU
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* specific headers are included.
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Joakim Gebart <joakim.gebart@eistec.se>
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*
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* @todo remove include irq.h once core was adjusted
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*/
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#ifndef CPU_H_
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#define CPU_H_
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#include "cpu_conf.h"
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#include "irq.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Configuration of default stack sizes
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*
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* As all members of the Cortex-M family behave identical in terms of stack
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* usage, we define the default stack size values here centrally for all CPU
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* implementations.
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*
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* If needed, you can overwrite these values the the `cpu_conf.h` file of the
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* specific CPU implementation.
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*
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* @todo Adjust values for Cortex-M4F with FPU?
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* @todo Configure second set if no newlib nano.specs are available?
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* @{
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*/
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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#define THREAD_EXTRA_STACKSIZE_PRINTF (512)
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#endif
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#ifndef THREAD_STACKSIZE_DEFAULT
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#define THREAD_STACKSIZE_DEFAULT (1024)
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#endif
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#ifndef THREAD_STACKSIZE_IDLE
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#define THREAD_STACKSIZE_IDLE (256)
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#endif
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/** @} */
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/**
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* @brief Deprecated interrupt control function for backward compatibility
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* @{
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*/
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#define eINT enableIRQ
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#define dINT disableIRQ
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/** @} */
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/**
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* @brief Some members of the Cortex-M family have architecture specific
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* atomic operations in atomic_arch.c
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*/
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#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
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defined(CPU_ARCH_CORTEX_M4F)
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#define ARCH_HAS_ATOMIC_COMPARE_AND_SWAP 1
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#endif
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/**
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* @brief Definition of available panic modes
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*/
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typedef enum {
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PANIC_NMI_HANDLER, /**< non maskable interrupt */
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PANIC_HARD_FAULT, /**< hard fault */
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#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
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defined(CPU_ARCH_CORTEX_M4F)
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PANIC_MEM_MANAGE, /**< memory controller interrupt */
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PANIC_BUS_FAULT, /**< bus fault */
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PANIC_USAGE_FAULT, /**< undefined instruction or unaligned access */
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PANIC_DEBUG_MON, /**< debug interrupt */
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#endif
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PANIC_DUMMY_HANDLER, /**< unhandled interrupt */
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} panic_t;
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/**
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* @brief Initialization of the CPU
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*/
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void cpu_init(void);
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/**
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* @brief Initialize Cortex-M specific core parts of the CPU
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*/
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void cortexm_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_H_ */
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/** @} */
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