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a2e1b92e1d
For RISC-V and Cortex-M-not-3, triples are known and have worked in some configuration, but do not work at the moment and stay disabled until the reference platforms (native, M3) have been established well.
18 lines
444 B
Makefile
18 lines
444 B
Makefile
ifeq ($(findstring rv32,$(CPU_CORE)),rv32)
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CPU_ARCH := rv32
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endif
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FEATURES_PROVIDED += arch_32bit
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FEATURES_PROVIDED += arch_riscv
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += libstdcpp
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FEATURES_PROVIDED += newlib
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FEATURES_PROVIDED += periph_coretimer
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#FEATURES_PROVIDED += rust_target
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FEATURES_PROVIDED += ssp
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# RISC-V toolchain on CI does not work properly with picolibc yet
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ifeq (,$(RIOT_CI_BUILD))
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FEATURES_PROVIDED += picolibc
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endif
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