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2ac0467807
This timer will be used by RIOT-OS as the scheduling timer for stm32mp157c-dk2 board. Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
86 lines
2.0 KiB
C
86 lines
2.0 KiB
C
/*
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* Copyright (C) 2020 Savoir-faire Linux
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Default STM32MP1 clock configuration for 208MHz boards
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*
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* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
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*/
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#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_208_H
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#define CLK_MP1_CFG_CLOCK_DEFAULT_208_H
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#include "mp1/cfg_clock_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (208MHz)
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* @{
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*/
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/* The following parameters configure a 208MHz system clock with HSE (24MHz)
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* or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (2)
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#endif
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24))
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (52)
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#endif
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#else /* HSI */
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (78)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (3)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (13)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (3)
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#endif
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/** @} */
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/**
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* @name Clock bus settings (MCU, APB1, APB2 and APB3)
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*/
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#ifndef CONFIG_CLOCK_MCU_DIV
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#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB3_DIV
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#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "mp1/cfg_clock_values.h"
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#if CLOCK_CORECLOCK > MHZ(208)
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#error "SYSCLK cannot exceed 208MHz"
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#endif
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#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_208_H */
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/** @} */
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