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https://github.com/RIOT-OS/RIOT.git
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230 lines
4.5 KiB
C
230 lines
4.5 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430fxyz
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "bitarithm.h"
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#include "periph/gpio.h"
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/**
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* @brief Number of possible interrupt lines: 2 ports * 8 pins
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*/
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#define ISR_NUMOF (16U)
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/**
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* @brief Number of pins on each port
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*/
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#define PINS_PER_PORT (8U)
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static msp_port_t *_port(gpio_t pin)
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{
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switch (pin >> 8) {
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case 1:
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return PORT_1;
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case 2:
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return PORT_2;
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case 3:
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return PORT_3;
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case 4:
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return PORT_4;
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case 5:
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return PORT_5;
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case 6:
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return PORT_6;
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default:
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return NULL;
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}
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}
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static inline uint8_t _pin(gpio_t pin)
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{
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return (uint8_t)(pin & 0xff);
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}
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static inline msp_port_isr_t *_isr_port(gpio_t pin)
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{
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msp_port_t *p = _port(pin);
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if ((p == PORT_1) || (p == PORT_2)) {
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return (msp_port_isr_t *)p;
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}
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return NULL;
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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msp_port_t *port = _port(pin);
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/* check if port is valid and mode applicable */
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if ((port == NULL) || ((mode != GPIO_IN) && (mode != GPIO_OUT))) {
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return -1;
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}
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/* set pin direction */
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if (mode == GPIO_OUT) {
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port->DIR |= _pin(pin);
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}
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else {
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port->DIR &= ~(_pin(pin));
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}
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return 0;
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}
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void gpio_periph_mode(gpio_t pin, bool enable)
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{
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REG8 *sel;
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msp_port_isr_t *isrport = _isr_port(pin);
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if (isrport) {
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sel = &(isrport->SEL);
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}
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else {
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msp_port_t *port = _port(pin);
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if (port) {
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sel = &(port->SEL);
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}
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else {
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return;
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}
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}
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if (enable) {
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*sel |= _pin(pin);
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}
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else {
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*sel &= ~(_pin(pin));
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}
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}
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int gpio_read(gpio_t pin)
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{
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msp_port_t *port = _port(pin);
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if (port->DIR & _pin(pin)) {
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return (int)(port->OD & _pin(pin));
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}
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else {
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return (int)(port->IN & _pin(pin));
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}
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}
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void gpio_set(gpio_t pin)
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{
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_port(pin)->OD |= _pin(pin);
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}
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void gpio_clear(gpio_t pin)
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{
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_port(pin)->OD &= ~(_pin(pin));
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}
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void gpio_toggle(gpio_t pin)
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{
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_port(pin)->OD ^= _pin(pin);
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value) {
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_port(pin)->OD |= _pin(pin);
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}
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else {
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_port(pin)->OD &= ~(_pin(pin));
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}
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}
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#ifdef MODULE_PERIPH_GPIO_IRQ
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/**
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* @brief Interrupt context for each interrupt line
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*/
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static gpio_isr_ctx_t isr_ctx[ISR_NUMOF];
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static int _ctx(gpio_t pin)
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{
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int i = bitarithm_lsb(_pin(pin));
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return (_port(pin) == PORT_1) ? i : (i + 8);
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}
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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msp_port_isr_t *port = _isr_port(pin);
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/* check if port, pull resistor and flank configuration are valid */
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if ((port == NULL) || (flank == GPIO_BOTH)) {
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return -1;
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}
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/* disable any activated interrupt */
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port->IE &= ~(_pin(pin));
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/* configure as input */
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if (gpio_init(pin, mode) < 0) {
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return -1;
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}
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/* save ISR context */
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isr_ctx[_ctx(pin)].cb = cb;
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isr_ctx[_ctx(pin)].arg = arg;
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/* configure flank */
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port->IES &= ~(_pin(pin));
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port->IES |= (flank & _pin(pin));
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/* clear pending interrupts and enable the IRQ */
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port->IFG &= ~(_pin(pin));
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gpio_irq_enable(pin);
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return 0;
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}
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void gpio_irq_enable(gpio_t pin)
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{
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msp_port_isr_t *port = _isr_port(pin);
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if (port) {
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port->IE |= _pin(pin);
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}
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}
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void gpio_irq_disable(gpio_t pin)
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{
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msp_port_isr_t *port = _isr_port(pin);
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if (port) {
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port->IE &= ~(_pin(pin));
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}
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}
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static inline void isr_handler(msp_port_isr_t *port, int ctx)
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{
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for (unsigned i = 0; i < PINS_PER_PORT; i++) {
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if ((port->IE & (1 << i)) && (port->IFG & (1 << i))) {
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port->IFG &= ~(1 << i);
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isr_ctx[i + ctx].cb(isr_ctx[i + ctx].arg);
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}
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}
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}
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ISR(PORT1_VECTOR, isr_port1)
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{
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__enter_isr();
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isr_handler((msp_port_isr_t *)PORT_1, 0);
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__exit_isr();
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}
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ISR(PORT2_VECTOR, isr_port2)
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{
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__enter_isr();
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isr_handler((msp_port_isr_t *)PORT_2, 8);
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__exit_isr();
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}
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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