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139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
// See LICENSE for license details.
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#ifndef _SIFIVE_PLATFORM_H
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#define _SIFIVE_PLATFORM_H
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// Some things missing from the official encoding.h
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#define MCAUSE_INT 0x80000000
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#define MCAUSE_CAUSE 0x7FFFFFFF
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#include "vendor/aon.h"
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#include "vendor/clint.h"
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#include "vendor/gpio.h"
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#include "vendor/i2c.h"
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#include "vendor/otp.h"
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#include "vendor/plic.h"
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#include "vendor/prci.h"
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#include "vendor/pwm.h"
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#include "vendor/spi.h"
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#include "vendor/uart.h"
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// Memory map
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#define MASKROM_MEM_ADDR (0x00001000)
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#define TRAPVEC_TABLE_CTRL_ADDR (0x00001010)
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#define OTP_MEM_ADDR (0x00020000)
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#define CLINT_CTRL_ADDR (0x02000000)
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#define ITIM_MEM_ADDR (0x08000000)
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#define PLIC_CTRL_ADDR (0x0C000000)
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#define AON_CTRL_ADDR (0x10000000)
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#define PRCI_CTRL_ADDR (0x10008000)
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#define OTP_CTRL_ADDR (0x10010000)
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#define GPIO_CTRL_ADDR (0x10012000)
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#define UART0_CTRL_ADDR (0x10013000)
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#define SPI0_CTRL_ADDR (0x10014000)
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#define PWM0_CTRL_ADDR (0x10015000)
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#define I2C0_CTRL_ADDR (0x10016000)
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#define UART1_CTRL_ADDR (0x10023000)
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#define SPI1_CTRL_ADDR (0x10024000)
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#define PWM1_CTRL_ADDR (0x10025000)
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#define SPI2_CTRL_ADDR (0x10034000)
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#define PWM2_CTRL_ADDR (0x10035000)
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#define SPI0_MEM_ADDR (0x20000000)
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#define MEM_CTRL_ADDR (0x80000000)
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// IOF masks
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#define IOF0_SPI1_MASK (0x000007FC)
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#define SPI11_NUM_SS (4)
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#define IOF_SPI1_SS0 (2u)
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#define IOF_SPI1_SS1 (8u)
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#define IOF_SPI1_SS2 (9u)
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#define IOF_SPI1_SS3 (10u)
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#define IOF_SPI1_MOSI (3u)
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#define IOF_SPI1_MISO (4u)
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#define IOF_SPI1_SCK (5u)
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#define IOF_SPI1_DQ0 (3u)
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#define IOF_SPI1_DQ1 (4u)
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#define IOF_SPI1_DQ2 (6u)
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#define IOF_SPI1_DQ3 (7u)
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#define IOF0_SPI2_MASK (0xFC000000)
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#define SPI2_NUM_SS (1)
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#define IOF_SPI2_SS0 (26u)
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#define IOF_SPI2_MOSI (27u)
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#define IOF_SPI2_MISO (28u)
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#define IOF_SPI2_SCK (29u)
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#define IOF_SPI2_DQ0 (27u)
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#define IOF_SPI2_DQ1 (28u)
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#define IOF_SPI2_DQ2 (30u)
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#define IOF_SPI2_DQ3 (31u)
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#define IOF0_I2C_MASK (0x00003000)
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#define IOF_I2C0_SDA (12u)
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#define IOF_I2C0_SCL (13u)
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#define IOF0_UART0_MASK (0x00030000)
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#define IOF_UART0_RX (16u)
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#define IOF_UART0_TX (17u)
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#define IOF0_UART1_MASK (0x00840000)
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#define IOF_UART1_RX (18u)
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#define IOF_UART1_TX (23u)
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#define IOF1_PWM0_MASK (0x0000000F)
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#define IOF1_PWM1_MASK (0x00780000)
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#define IOF1_PWM2_MASK (0x00003C00)
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// Interrupt numbers
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#define INT_RESERVED 0
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#define INT_WDOGCMP 1
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#define INT_RTCCMP 2
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#define INT_UART0_BASE 3
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#define INT_UART1_BASE 4
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#define INT_SPI0_BASE 5
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#define INT_SPI1_BASE 6
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#define INT_SPI2_BASE 7
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#define INT_GPIO_BASE 8
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#define INT_PWM0_BASE 40
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#define INT_PWM1_BASE 44
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#define INT_PWM2_BASE 48
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#define INT_I2C_BASE 52
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// Helper functions
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#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
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#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
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#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
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#define I2C0_REG(offset) _REG32(I2C0_CTRL_ADDR, offset)
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#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
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#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
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#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
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#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
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#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
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#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
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#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
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#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
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#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
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#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
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#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
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// Misc
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#define NUM_GPIO 32
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#define PLIC_NUM_INTERRUPTS 52
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#define PLIC_NUM_PRIORITIES 7
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#define RTC_FREQ 32768
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#define ITIM_MEM_LEN 8192
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#endif /* _SIFIVE_PLATFORM_H */
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