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559 lines
29 KiB
C
559 lines
29 KiB
C
/**
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* \file
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*
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* \brief Header file for SAMR21E16A
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*
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* Copyright (c) 2017 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMR21E16A_
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#define _SAMR21E16A_
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/**
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* \ingroup SAMR21_definitions
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* \addtogroup SAMR21E16A_definitions SAMR21E16A definitions
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* This file defines all structures and symbols for SAMR21E16A:
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* - registers and bitfields
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* - peripheral base address
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* - peripheral ID
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* - PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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#define CAST(type, value) ((type *)(value))
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#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
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#else
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#define CAST(type, value) (value)
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#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
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#endif
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/* ************************************************************************** */
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/** CMSIS DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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/** \defgroup SAMR21E16A_cmsis CMSIS Definitions */
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/*@{*/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
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NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
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PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
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/****** SAMR21E16A-specific Interrupt Numbers ***********************/
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PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */
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SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */
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WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */
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RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */
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EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */
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NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */
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DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */
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USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */
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EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */
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SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */
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SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */
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SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */
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SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */
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SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */
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SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */
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TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */
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TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */
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TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */
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TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */
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TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */
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TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */
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ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */
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AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */
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PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */
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PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
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} IRQn_Type;
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typedef struct _DeviceVectors
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{
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/* Stack pointer */
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void* pvStack;
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/* Cortex-M handlers */
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void* pfnReset_Handler;
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void* pfnNMI_Handler;
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void* pfnHardFault_Handler;
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void* pfnReservedM12;
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void* pfnReservedM11;
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void* pfnReservedM10;
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void* pfnReservedM9;
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void* pfnReservedM8;
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void* pfnReservedM7;
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void* pfnReservedM6;
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void* pfnSVC_Handler;
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void* pfnReservedM4;
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void* pfnReservedM3;
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void* pfnPendSV_Handler;
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void* pfnSysTick_Handler;
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/* Peripheral handlers */
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void* pfnPM_Handler; /* 0 Power Manager */
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void* pfnSYSCTRL_Handler; /* 1 System Control */
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void* pfnWDT_Handler; /* 2 Watchdog Timer */
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void* pfnRTC_Handler; /* 3 Real-Time Counter */
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void* pfnEIC_Handler; /* 4 External Interrupt Controller */
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void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
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void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
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void* pfnUSB_Handler; /* 7 Universal Serial Bus */
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void* pfnEVSYS_Handler; /* 8 Event System Interface */
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void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
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void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
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void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
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void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
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void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
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void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
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void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
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void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
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void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
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void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
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void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
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void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
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void* pfnReserved21;
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void* pfnReserved22;
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void* pfnADC_Handler; /* 23 Analog Digital Converter */
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void* pfnAC_Handler; /* 24 Analog Comparators */
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void* pfnReserved25;
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void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
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void* pfnReserved27;
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void* pfnReserved28;
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} DeviceVectors;
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/* Cortex-M0+ processor handlers */
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void Reset_Handler ( void );
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void NMI_Handler ( void );
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void HardFault_Handler ( void );
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void SVC_Handler ( void );
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void PendSV_Handler ( void );
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void SysTick_Handler ( void );
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/* Peripherals handlers */
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void PM_Handler ( void );
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void SYSCTRL_Handler ( void );
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void WDT_Handler ( void );
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void RTC_Handler ( void );
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void EIC_Handler ( void );
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void NVMCTRL_Handler ( void );
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void DMAC_Handler ( void );
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void USB_Handler ( void );
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void EVSYS_Handler ( void );
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void SERCOM0_Handler ( void );
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void SERCOM1_Handler ( void );
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void SERCOM2_Handler ( void );
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void SERCOM3_Handler ( void );
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void SERCOM4_Handler ( void );
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void SERCOM5_Handler ( void );
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void TCC0_Handler ( void );
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void TCC1_Handler ( void );
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void TCC2_Handler ( void );
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void TC3_Handler ( void );
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void TC4_Handler ( void );
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void TC5_Handler ( void );
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void ADC_Handler ( void );
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void AC_Handler ( void );
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void PTC_Handler ( void );
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/*
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* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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*/
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#define LITTLE_ENDIAN 1
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#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
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#define __VTOR_PRESENT 1 /*!< VTOR present or not */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* \brief CMSIS includes
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*/
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#include <core_cm0plus.h>
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#if !defined DONT_USE_CMSIS_INIT
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#include "system_samr21.h"
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#endif /* DONT_USE_CMSIS_INIT */
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E16A */
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/* ************************************************************************** */
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/** \defgroup SAMR21E16A_api Peripheral Software API */
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/*@{*/
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#include "component/ac.h"
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#include "component/adc.h"
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#include "component/dmac.h"
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#include "component/dsu.h"
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#include "component/eic.h"
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#include "component/evsys.h"
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#include "component/gclk.h"
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#include "component/hmatrixb.h"
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#include "component/mtb.h"
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#include "component/nvmctrl.h"
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#include "component/pac.h"
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#include "component/pm.h"
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#include "component/port.h"
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#include "component/rfctrl.h"
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#include "component/rtc.h"
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#include "component/sercom.h"
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#include "component/sysctrl.h"
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#include "component/tc.h"
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#include "component/tcc.h"
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#include "component/usb.h"
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#include "component/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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/** \defgroup SAMR21E16A_reg Registers Access Definitions */
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/*@{*/
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#include "instance/ac.h"
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#include "instance/adc.h"
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#include "instance/dmac.h"
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#include "instance/dsu.h"
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#include "instance/eic.h"
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#include "instance/evsys.h"
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#include "instance/gclk.h"
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#include "instance/sbmatrix.h"
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#include "instance/mtb.h"
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#include "instance/nvmctrl.h"
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#include "instance/pac0.h"
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#include "instance/pac1.h"
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#include "instance/pac2.h"
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#include "instance/pm.h"
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#include "instance/port.h"
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#include "instance/rfctrl.h"
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#include "instance/rtc.h"
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#include "instance/sercom0.h"
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#include "instance/sercom1.h"
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#include "instance/sercom2.h"
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#include "instance/sercom3.h"
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#include "instance/sercom4.h"
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#include "instance/sercom5.h"
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#include "instance/sysctrl.h"
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#include "instance/tc3.h"
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#include "instance/tc4.h"
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#include "instance/tc5.h"
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#include "instance/tcc0.h"
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#include "instance/tcc1.h"
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#include "instance/tcc2.h"
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#include "instance/usb.h"
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#include "instance/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** PERIPHERAL ID DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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/** \defgroup SAMR21E16A_id Peripheral Ids Definitions */
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/*@{*/
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// Peripheral instances on HPB0 bridge
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#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
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#define ID_PM 1 /**< \brief Power Manager (PM) */
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#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
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#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
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#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
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#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
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#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
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// Peripheral instances on HPB1 bridge
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#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
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#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
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#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
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#define ID_PORT 35 /**< \brief Port Module (PORT) */
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#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
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#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
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#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
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#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
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// Peripheral instances on HPB2 bridge
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#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
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#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
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#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
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#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
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#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
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#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
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#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
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#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
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#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
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#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
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#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
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#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
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#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
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#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
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#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
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#define ID_AC 81 /**< \brief Analog Comparators (AC) */
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#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
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#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
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#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
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/*@}*/
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/* ************************************************************************** */
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/** BASE ADDRESS DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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/** \defgroup SAMR21E16A_base Peripheral Base Address Definitions */
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/*@{*/
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#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
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#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
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#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
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#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
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#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
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#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
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#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
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#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
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#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
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#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
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#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
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#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
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#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
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#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
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#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
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#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
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#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */
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#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
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#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
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#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
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#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
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#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
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#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
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#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
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#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
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#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
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#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
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#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
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#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
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#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
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#else
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#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
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#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
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#define AC_INSTS { AC } /**< \brief (AC) Instances List */
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#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
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#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
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#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
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#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
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#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
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#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
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#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
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#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
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#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
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#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
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#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
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#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
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#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
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#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
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#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
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#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
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#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
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#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
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#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
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#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
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#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
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#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
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#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
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#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
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#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
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#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
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#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
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#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
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#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
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#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
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#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
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#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
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#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
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#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
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#define PM_INSTS { PM } /**< \brief (PM) Instances List */
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#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
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#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
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#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
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#define PTC_GCLK_ID 34
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#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
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#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
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#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */
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#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
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#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
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#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
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#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
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#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
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#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
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#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
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#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
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#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
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#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
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#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
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#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
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#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
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#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
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#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
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#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
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#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
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#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
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#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
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#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
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#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
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#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
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#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
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#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
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#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
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#define USB_INSTS { USB } /**< \brief (USB) Instances List */
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#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
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#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
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#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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/* ************************************************************************** */
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/** PORT DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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/** \defgroup SAMR21E16A_port PORT Definitions */
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/*@{*/
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#include "pio/samr21e16a.h"
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/*@}*/
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/* ************************************************************************** */
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/** MEMORY MAPPING DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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#define FLASH_SIZE 0x10000UL /* 64 kB */
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#define FLASH_PAGE_SIZE 64
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#define FLASH_NB_OF_PAGES 1024
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#define FLASH_USER_PAGE_SIZE 64
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#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
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#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
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#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
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#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
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#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
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#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
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#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
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#define PPB_ADDR (0xE0000000u) /**< PPB base address */
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#define DSU_DID_RESETVALUE 0x1001001EUL
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#define EIC_EXTINT_NUM 16
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#define PORT_GROUPS 3
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#define SIP_CONFIG RF233
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/* ************************************************************************** */
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/** ELECTRICAL DEFINITIONS FOR SAMR21E16A */
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/* ************************************************************************** */
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif /* SAMR21E16A_H */
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