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145 lines
9.7 KiB
C
145 lines
9.7 KiB
C
/**
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* \file
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*
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* \brief Instance description for PORT
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_PORT_INSTANCE_
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#define _SAML21_PORT_INSTANCE_
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/* ========== Register definition for PORT peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PORT_DIR0 (0x40002800U) /**< \brief (PORT) Data Direction 0 */
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#define REG_PORT_DIRCLR0 (0x40002804U) /**< \brief (PORT) Data Direction Clear 0 */
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#define REG_PORT_DIRSET0 (0x40002808U) /**< \brief (PORT) Data Direction Set 0 */
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#define REG_PORT_DIRTGL0 (0x4000280CU) /**< \brief (PORT) Data Direction Toggle 0 */
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#define REG_PORT_OUT0 (0x40002810U) /**< \brief (PORT) Data Output Value 0 */
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#define REG_PORT_OUTCLR0 (0x40002814U) /**< \brief (PORT) Data Output Value Clear 0 */
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#define REG_PORT_OUTSET0 (0x40002818U) /**< \brief (PORT) Data Output Value Set 0 */
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#define REG_PORT_OUTTGL0 (0x4000281CU) /**< \brief (PORT) Data Output Value Toggle 0 */
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#define REG_PORT_IN0 (0x40002820U) /**< \brief (PORT) Data Input Value 0 */
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#define REG_PORT_CTRL0 (0x40002824U) /**< \brief (PORT) Control 0 */
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#define REG_PORT_WRCONFIG0 (0x40002828U) /**< \brief (PORT) Write Configuration 0 */
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#define REG_PORT_EVCTRL0 (0x4000282CU) /**< \brief (PORT) Event Input Control 0 */
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#define REG_PORT_PMUX0 (0x40002830U) /**< \brief (PORT) Peripheral Multiplexing 0 */
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#define REG_PORT_PINCFG0 (0x40002840U) /**< \brief (PORT) Pin Configuration 0 */
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#define REG_PORT_DIR1 (0x40002880U) /**< \brief (PORT) Data Direction 1 */
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#define REG_PORT_DIRCLR1 (0x40002884U) /**< \brief (PORT) Data Direction Clear 1 */
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#define REG_PORT_DIRSET1 (0x40002888U) /**< \brief (PORT) Data Direction Set 1 */
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#define REG_PORT_DIRTGL1 (0x4000288CU) /**< \brief (PORT) Data Direction Toggle 1 */
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#define REG_PORT_OUT1 (0x40002890U) /**< \brief (PORT) Data Output Value 1 */
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#define REG_PORT_OUTCLR1 (0x40002894U) /**< \brief (PORT) Data Output Value Clear 1 */
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#define REG_PORT_OUTSET1 (0x40002898U) /**< \brief (PORT) Data Output Value Set 1 */
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#define REG_PORT_OUTTGL1 (0x4000289CU) /**< \brief (PORT) Data Output Value Toggle 1 */
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#define REG_PORT_IN1 (0x400028A0U) /**< \brief (PORT) Data Input Value 1 */
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#define REG_PORT_CTRL1 (0x400028A4U) /**< \brief (PORT) Control 1 */
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#define REG_PORT_WRCONFIG1 (0x400028A8U) /**< \brief (PORT) Write Configuration 1 */
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#define REG_PORT_EVCTRL1 (0x400028ACU) /**< \brief (PORT) Event Input Control 1 */
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#define REG_PORT_PMUX1 (0x400028B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
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#define REG_PORT_PINCFG1 (0x400028C0U) /**< \brief (PORT) Pin Configuration 1 */
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#else
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#define REG_PORT_DIR0 (*(RwReg *)0x40002800U) /**< \brief (PORT) Data Direction 0 */
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#define REG_PORT_DIRCLR0 (*(RwReg *)0x40002804U) /**< \brief (PORT) Data Direction Clear 0 */
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#define REG_PORT_DIRSET0 (*(RwReg *)0x40002808U) /**< \brief (PORT) Data Direction Set 0 */
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#define REG_PORT_DIRTGL0 (*(RwReg *)0x4000280CU) /**< \brief (PORT) Data Direction Toggle 0 */
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#define REG_PORT_OUT0 (*(RwReg *)0x40002810U) /**< \brief (PORT) Data Output Value 0 */
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#define REG_PORT_OUTCLR0 (*(RwReg *)0x40002814U) /**< \brief (PORT) Data Output Value Clear 0 */
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#define REG_PORT_OUTSET0 (*(RwReg *)0x40002818U) /**< \brief (PORT) Data Output Value Set 0 */
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#define REG_PORT_OUTTGL0 (*(RwReg *)0x4000281CU) /**< \brief (PORT) Data Output Value Toggle 0 */
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#define REG_PORT_IN0 (*(RoReg *)0x40002820U) /**< \brief (PORT) Data Input Value 0 */
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#define REG_PORT_CTRL0 (*(RwReg *)0x40002824U) /**< \brief (PORT) Control 0 */
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#define REG_PORT_WRCONFIG0 (*(WoReg *)0x40002828U) /**< \brief (PORT) Write Configuration 0 */
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#define REG_PORT_EVCTRL0 (*(RwReg *)0x4000282CU) /**< \brief (PORT) Event Input Control 0 */
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#define REG_PORT_PMUX0 (*(RwReg *)0x40002830U) /**< \brief (PORT) Peripheral Multiplexing 0 */
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#define REG_PORT_PINCFG0 (*(RwReg *)0x40002840U) /**< \brief (PORT) Pin Configuration 0 */
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#define REG_PORT_DIR1 (*(RwReg *)0x40002880U) /**< \brief (PORT) Data Direction 1 */
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#define REG_PORT_DIRCLR1 (*(RwReg *)0x40002884U) /**< \brief (PORT) Data Direction Clear 1 */
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#define REG_PORT_DIRSET1 (*(RwReg *)0x40002888U) /**< \brief (PORT) Data Direction Set 1 */
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#define REG_PORT_DIRTGL1 (*(RwReg *)0x4000288CU) /**< \brief (PORT) Data Direction Toggle 1 */
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#define REG_PORT_OUT1 (*(RwReg *)0x40002890U) /**< \brief (PORT) Data Output Value 1 */
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#define REG_PORT_OUTCLR1 (*(RwReg *)0x40002894U) /**< \brief (PORT) Data Output Value Clear 1 */
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#define REG_PORT_OUTSET1 (*(RwReg *)0x40002898U) /**< \brief (PORT) Data Output Value Set 1 */
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#define REG_PORT_OUTTGL1 (*(RwReg *)0x4000289CU) /**< \brief (PORT) Data Output Value Toggle 1 */
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#define REG_PORT_IN1 (*(RoReg *)0x400028A0U) /**< \brief (PORT) Data Input Value 1 */
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#define REG_PORT_CTRL1 (*(RwReg *)0x400028A4U) /**< \brief (PORT) Control 1 */
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#define REG_PORT_WRCONFIG1 (*(WoReg *)0x400028A8U) /**< \brief (PORT) Write Configuration 1 */
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#define REG_PORT_EVCTRL1 (*(RwReg *)0x400028ACU) /**< \brief (PORT) Event Input Control 1 */
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#define REG_PORT_PMUX1 (*(RwReg *)0x400028B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
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#define REG_PORT_PINCFG1 (*(RwReg *)0x400028C0U) /**< \brief (PORT) Pin Configuration 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PORT peripheral ========== */
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#define PORT_BITS 84
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#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_DRVSTR 1 // DRVSTR supported?
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#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 }
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#define PORT_EV_NUM 4
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#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_ODRAIN 0 // ODRAIN supported?
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#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x000D0000 }
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#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x00000000 }
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#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
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#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 }
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#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x000D0000 }
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#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 }
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#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CFC7, 0x00000000 }
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#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
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#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
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#define PORT_SLEWLIM 0 // SLEWLIM supported?
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#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
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#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
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#endif /* _SAML21_PORT_INSTANCE_ */
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