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92 lines
5.7 KiB
C
92 lines
5.7 KiB
C
/**
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* \file
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*
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* \brief Instance description for PAC
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_PAC_INSTANCE_
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#define _SAML21_PAC_INSTANCE_
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/* ========== Register definition for PAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PAC_WRCTRL (0x44000000U) /**< \brief (PAC) Write control */
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#define REG_PAC_EVCTRL (0x44000004U) /**< \brief (PAC) Event control */
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#define REG_PAC_INTENCLR (0x44000008U) /**< \brief (PAC) Interrupt enable clear */
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#define REG_PAC_INTENSET (0x44000009U) /**< \brief (PAC) Interrupt enable set */
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#define REG_PAC_INTFLAGAHB (0x44000010U) /**< \brief (PAC) Bridge interrupt flag status */
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#define REG_PAC_INTFLAGA (0x44000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
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#define REG_PAC_INTFLAGB (0x44000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
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#define REG_PAC_INTFLAGC (0x4400001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
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#define REG_PAC_INTFLAGD (0x44000020U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
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#define REG_PAC_INTFLAGE (0x44000024U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */
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#define REG_PAC_STATUSA (0x44000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */
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#define REG_PAC_STATUSB (0x44000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */
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#define REG_PAC_STATUSC (0x4400003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */
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#define REG_PAC_STATUSD (0x44000040U) /**< \brief (PAC) Peripheral write protection status - Bridge D */
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#define REG_PAC_STATUSE (0x44000044U) /**< \brief (PAC) Peripheral write protection status - Bridge E */
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#else
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#define REG_PAC_WRCTRL (*(RwReg *)0x44000000U) /**< \brief (PAC) Write control */
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#define REG_PAC_EVCTRL (*(RwReg8 *)0x44000004U) /**< \brief (PAC) Event control */
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#define REG_PAC_INTENCLR (*(RwReg8 *)0x44000008U) /**< \brief (PAC) Interrupt enable clear */
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#define REG_PAC_INTENSET (*(RwReg8 *)0x44000009U) /**< \brief (PAC) Interrupt enable set */
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#define REG_PAC_INTFLAGAHB (*(RwReg *)0x44000010U) /**< \brief (PAC) Bridge interrupt flag status */
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#define REG_PAC_INTFLAGA (*(RwReg *)0x44000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
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#define REG_PAC_INTFLAGB (*(RwReg *)0x44000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
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#define REG_PAC_INTFLAGC (*(RwReg *)0x4400001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
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#define REG_PAC_INTFLAGD (*(RwReg *)0x44000020U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
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#define REG_PAC_INTFLAGE (*(RwReg *)0x44000024U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */
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#define REG_PAC_STATUSA (*(RoReg *)0x44000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */
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#define REG_PAC_STATUSB (*(RoReg *)0x44000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */
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#define REG_PAC_STATUSC (*(RoReg *)0x4400003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */
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#define REG_PAC_STATUSD (*(RoReg *)0x44000040U) /**< \brief (PAC) Peripheral write protection status - Bridge D */
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#define REG_PAC_STATUSE (*(RoReg *)0x44000044U) /**< \brief (PAC) Peripheral write protection status - Bridge E */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PAC peripheral ========== */
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#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
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#define PAC_CLK_AHB_ID 14 // AHB clock index
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#define PAC_HPB_NUM 5 // Number of bridges AHB/APB
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#define PAC_INTFLAG_NUM 6 // Number of intflag registers
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#endif /* _SAML21_PAC_INSTANCE_ */
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