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114 lines
7.3 KiB
C
114 lines
7.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for DMAC
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_DMAC_INSTANCE_
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#define _SAML21_DMAC_INSTANCE_
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/* ========== Register definition for DMAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DMAC_CTRL (0x44000400U) /**< \brief (DMAC) Control */
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#define REG_DMAC_CRCCTRL (0x44000402U) /**< \brief (DMAC) CRC Control */
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#define REG_DMAC_CRCDATAIN (0x44000404U) /**< \brief (DMAC) CRC Data Input */
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#define REG_DMAC_CRCCHKSUM (0x44000408U) /**< \brief (DMAC) CRC Checksum */
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#define REG_DMAC_CRCSTATUS (0x4400040CU) /**< \brief (DMAC) CRC Status */
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#define REG_DMAC_DBGCTRL (0x4400040DU) /**< \brief (DMAC) Debug Control */
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#define REG_DMAC_SWTRIGCTRL (0x44000410U) /**< \brief (DMAC) Software Trigger Control */
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#define REG_DMAC_PRICTRL0 (0x44000414U) /**< \brief (DMAC) Priority Control 0 */
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#define REG_DMAC_INTPEND (0x44000420U) /**< \brief (DMAC) Interrupt Pending */
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#define REG_DMAC_INTSTATUS (0x44000424U) /**< \brief (DMAC) Interrupt Status */
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#define REG_DMAC_BUSYCH (0x44000428U) /**< \brief (DMAC) Busy Channels */
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#define REG_DMAC_PENDCH (0x4400042CU) /**< \brief (DMAC) Pending Channels */
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#define REG_DMAC_ACTIVE (0x44000430U) /**< \brief (DMAC) Active Channel and Levels */
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#define REG_DMAC_BASEADDR (0x44000434U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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#define REG_DMAC_WRBADDR (0x44000438U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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#define REG_DMAC_CHID (0x4400043FU) /**< \brief (DMAC) Channel ID */
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#define REG_DMAC_CHCTRLA (0x44000440U) /**< \brief (DMAC) Channel Control A */
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#define REG_DMAC_CHCTRLB (0x44000444U) /**< \brief (DMAC) Channel Control B */
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#define REG_DMAC_CHINTENCLR (0x4400044CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
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#define REG_DMAC_CHINTENSET (0x4400044DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
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#define REG_DMAC_CHINTFLAG (0x4400044EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
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#define REG_DMAC_CHSTATUS (0x4400044FU) /**< \brief (DMAC) Channel Status */
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#else
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#define REG_DMAC_CTRL (*(RwReg16*)0x44000400U) /**< \brief (DMAC) Control */
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#define REG_DMAC_CRCCTRL (*(RwReg16*)0x44000402U) /**< \brief (DMAC) CRC Control */
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#define REG_DMAC_CRCDATAIN (*(RwReg *)0x44000404U) /**< \brief (DMAC) CRC Data Input */
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#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x44000408U) /**< \brief (DMAC) CRC Checksum */
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#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4400040CU) /**< \brief (DMAC) CRC Status */
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#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4400040DU) /**< \brief (DMAC) Debug Control */
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#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x44000410U) /**< \brief (DMAC) Software Trigger Control */
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#define REG_DMAC_PRICTRL0 (*(RwReg *)0x44000414U) /**< \brief (DMAC) Priority Control 0 */
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#define REG_DMAC_INTPEND (*(RwReg16*)0x44000420U) /**< \brief (DMAC) Interrupt Pending */
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#define REG_DMAC_INTSTATUS (*(RoReg *)0x44000424U) /**< \brief (DMAC) Interrupt Status */
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#define REG_DMAC_BUSYCH (*(RoReg *)0x44000428U) /**< \brief (DMAC) Busy Channels */
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#define REG_DMAC_PENDCH (*(RoReg *)0x4400042CU) /**< \brief (DMAC) Pending Channels */
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#define REG_DMAC_ACTIVE (*(RoReg *)0x44000430U) /**< \brief (DMAC) Active Channel and Levels */
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#define REG_DMAC_BASEADDR (*(RwReg *)0x44000434U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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#define REG_DMAC_WRBADDR (*(RwReg *)0x44000438U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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#define REG_DMAC_CHID (*(RwReg8 *)0x4400043FU) /**< \brief (DMAC) Channel ID */
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#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x44000440U) /**< \brief (DMAC) Channel Control A */
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#define REG_DMAC_CHCTRLB (*(RwReg *)0x44000444U) /**< \brief (DMAC) Channel Control B */
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#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4400044CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
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#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4400044DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
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#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4400044EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
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#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4400044FU) /**< \brief (DMAC) Channel Status */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DMAC peripheral ========== */
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#define DMAC_CH_BITS 4 // Number of bits to select channel
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#define DMAC_CH_NUM 16 // Number of channels
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#define DMAC_CLK_AHB_ID 11 // AHB clock index
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#define DMAC_EVIN_NUM 8 // Number of input events
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#define DMAC_EVOUT_NUM 8 // Number of output events
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#define DMAC_LVL_BITS 2 // Number of bit to select level priority
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#define DMAC_LVL_NUM 4 // Enable priority level number
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#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
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#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
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#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
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#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
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#define DMAC_TRIG_NUM 46 // Number of peripheral triggers
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#endif /* _SAML21_DMAC_INSTANCE_ */
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