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120 lines
7.6 KiB
C
120 lines
7.6 KiB
C
/**
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* \file
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*
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* \brief Instance description for AES
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_AES_INSTANCE_
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#define _SAML21_AES_INSTANCE_
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/* ========== Register definition for AES peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_AES_CTRLA (0x42003400U) /**< \brief (AES) Control A */
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#define REG_AES_CTRLB (0x42003404U) /**< \brief (AES) Control B */
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#define REG_AES_INTENCLR (0x42003405U) /**< \brief (AES) Interrupt Enable Clear */
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#define REG_AES_INTENSET (0x42003406U) /**< \brief (AES) Interrupt Enable Set */
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#define REG_AES_INTFLAG (0x42003407U) /**< \brief (AES) Interrupt Flag Status */
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#define REG_AES_DATABUFPTR (0x42003408U) /**< \brief (AES) Data buffer pointer */
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#define REG_AES_DBGCTRL (0x42003409U) /**< \brief (AES) Debug control */
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#define REG_AES_KEYWORD0 (0x4200340CU) /**< \brief (AES) Keyword 0 */
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#define REG_AES_KEYWORD1 (0x42003410U) /**< \brief (AES) Keyword 1 */
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#define REG_AES_KEYWORD2 (0x42003414U) /**< \brief (AES) Keyword 2 */
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#define REG_AES_KEYWORD3 (0x42003418U) /**< \brief (AES) Keyword 3 */
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#define REG_AES_KEYWORD4 (0x4200341CU) /**< \brief (AES) Keyword 4 */
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#define REG_AES_KEYWORD5 (0x42003420U) /**< \brief (AES) Keyword 5 */
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#define REG_AES_KEYWORD6 (0x42003424U) /**< \brief (AES) Keyword 6 */
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#define REG_AES_KEYWORD7 (0x42003428U) /**< \brief (AES) Keyword 7 */
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#define REG_AES_INDATA (0x42003438U) /**< \brief (AES) Indata */
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#define REG_AES_INTVECTV0 (0x4200343CU) /**< \brief (AES) Initialisation Vector 0 */
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#define REG_AES_INTVECTV1 (0x42003440U) /**< \brief (AES) Initialisation Vector 1 */
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#define REG_AES_INTVECTV2 (0x42003444U) /**< \brief (AES) Initialisation Vector 2 */
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#define REG_AES_INTVECTV3 (0x42003448U) /**< \brief (AES) Initialisation Vector 3 */
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#define REG_AES_HASHKEY0 (0x4200345CU) /**< \brief (AES) Hash key 0 */
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#define REG_AES_HASHKEY1 (0x42003460U) /**< \brief (AES) Hash key 1 */
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#define REG_AES_HASHKEY2 (0x42003464U) /**< \brief (AES) Hash key 2 */
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#define REG_AES_HASHKEY3 (0x42003468U) /**< \brief (AES) Hash key 3 */
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#define REG_AES_GHASH0 (0x4200346CU) /**< \brief (AES) Galois Hash 0 */
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#define REG_AES_GHASH1 (0x42003470U) /**< \brief (AES) Galois Hash 1 */
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#define REG_AES_GHASH2 (0x42003474U) /**< \brief (AES) Galois Hash 2 */
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#define REG_AES_GHASH3 (0x42003478U) /**< \brief (AES) Galois Hash 3 */
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#define REG_AES_CIPLEN (0x42003480U) /**< \brief (AES) Cipher Length */
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#define REG_AES_RANDSEED (0x42003484U) /**< \brief (AES) Random Seed */
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#else
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#define REG_AES_CTRLA (*(RwReg *)0x42003400U) /**< \brief (AES) Control A */
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#define REG_AES_CTRLB (*(RwReg8 *)0x42003404U) /**< \brief (AES) Control B */
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#define REG_AES_INTENCLR (*(RwReg8 *)0x42003405U) /**< \brief (AES) Interrupt Enable Clear */
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#define REG_AES_INTENSET (*(RwReg8 *)0x42003406U) /**< \brief (AES) Interrupt Enable Set */
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#define REG_AES_INTFLAG (*(RwReg8 *)0x42003407U) /**< \brief (AES) Interrupt Flag Status */
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#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42003408U) /**< \brief (AES) Data buffer pointer */
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#define REG_AES_DBGCTRL (*(WoReg8 *)0x42003409U) /**< \brief (AES) Debug control */
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#define REG_AES_KEYWORD0 (*(WoReg *)0x4200340CU) /**< \brief (AES) Keyword 0 */
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#define REG_AES_KEYWORD1 (*(WoReg *)0x42003410U) /**< \brief (AES) Keyword 1 */
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#define REG_AES_KEYWORD2 (*(WoReg *)0x42003414U) /**< \brief (AES) Keyword 2 */
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#define REG_AES_KEYWORD3 (*(WoReg *)0x42003418U) /**< \brief (AES) Keyword 3 */
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#define REG_AES_KEYWORD4 (*(WoReg *)0x4200341CU) /**< \brief (AES) Keyword 4 */
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#define REG_AES_KEYWORD5 (*(WoReg *)0x42003420U) /**< \brief (AES) Keyword 5 */
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#define REG_AES_KEYWORD6 (*(WoReg *)0x42003424U) /**< \brief (AES) Keyword 6 */
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#define REG_AES_KEYWORD7 (*(WoReg *)0x42003428U) /**< \brief (AES) Keyword 7 */
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#define REG_AES_INDATA (*(RwReg *)0x42003438U) /**< \brief (AES) Indata */
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#define REG_AES_INTVECTV0 (*(WoReg *)0x4200343CU) /**< \brief (AES) Initialisation Vector 0 */
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#define REG_AES_INTVECTV1 (*(WoReg *)0x42003440U) /**< \brief (AES) Initialisation Vector 1 */
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#define REG_AES_INTVECTV2 (*(WoReg *)0x42003444U) /**< \brief (AES) Initialisation Vector 2 */
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#define REG_AES_INTVECTV3 (*(WoReg *)0x42003448U) /**< \brief (AES) Initialisation Vector 3 */
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#define REG_AES_HASHKEY0 (*(RwReg *)0x4200345CU) /**< \brief (AES) Hash key 0 */
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#define REG_AES_HASHKEY1 (*(RwReg *)0x42003460U) /**< \brief (AES) Hash key 1 */
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#define REG_AES_HASHKEY2 (*(RwReg *)0x42003464U) /**< \brief (AES) Hash key 2 */
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#define REG_AES_HASHKEY3 (*(RwReg *)0x42003468U) /**< \brief (AES) Hash key 3 */
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#define REG_AES_GHASH0 (*(RwReg *)0x4200346CU) /**< \brief (AES) Galois Hash 0 */
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#define REG_AES_GHASH1 (*(RwReg *)0x42003470U) /**< \brief (AES) Galois Hash 1 */
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#define REG_AES_GHASH2 (*(RwReg *)0x42003474U) /**< \brief (AES) Galois Hash 2 */
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#define REG_AES_GHASH3 (*(RwReg *)0x42003478U) /**< \brief (AES) Galois Hash 3 */
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#define REG_AES_CIPLEN (*(RwReg *)0x42003480U) /**< \brief (AES) Cipher Length */
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#define REG_AES_RANDSEED (*(RwReg *)0x42003484U) /**< \brief (AES) Random Seed */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for AES peripheral ========== */
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#define AES_DMAC_ID_RD 45 // DMA DATA Read trigger
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#define AES_DMAC_ID_WR 44 // DMA DATA Write trigger
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#endif /* _SAML21_AES_INSTANCE_ */
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