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d35511bee7
This adds a driver for the SPI based AT86RF215 transceiver.
The chip supports the IEEE Std 802.15.4-2015 and IEEE Std 802.15.4g-2012 standard.
This driver supports two versions of the chip:
- AT86RF215: dual sub-GHz & 2.4 GHz radio & baseband
- AT86RF215M: sub-GHz radio & baseband only
Both radios support the following PHY modes:
- MR-FSK
- MR-OFDM
- MR-O-QPKS
- O-QPSK (legacy)
The driver currently only implements support for legacy O-QPSK.
To use both interfaces, add
GNRC_NETIF_NUMOF := 2
to your Makefile.
The transceiver is able to send frames of up to 2047 bytes according to
IEEE 802.15.4g-2012 when operating in non-legacy mode.
Known issues:
- [ ] dBm setting values are bogus
- [ ] Channel spacing for sub-GHz MR-O-QPSK might be wrong
- [ ] TX/RX stress test will lock up the driver on openmote-b
278 lines
7.9 KiB
C
278 lines
7.9 KiB
C
/*
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* Copyright (C) 2019 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_at86rf215
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* @{
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*
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* @file
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* @brief Configuration of the MR-O-QPSK PHY on the AT86RF215 chip
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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* @}
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*/
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#include "at86rf215.h"
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#include "at86rf215_internal.h"
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#include "debug.h"
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/* IEEE Std 802.15.4g™-2012 Amendment 3
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* Table 68d—Total number of channels and first channel center frequencies for SUN PHYs
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* Table 68e—Center frequencies for the MR-O-QPSK PHY operating in the 868–870 MHz band
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*/
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/* currently only EU-868 MHz band is supported */
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#define QPSK_CHANNEL_SPACING_SUBGHZ (650U) /* kHz */
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#define QPSK_CENTER_FREQUENCY_SUBGHZ (868300U) /* Hz */
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#define QPSK_CHANNEL_SPACING_24GHZ (5000U) /* kHz */
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#define QPSK_CENTER_FREQUENCY_24GHZ (2350000U - CCF0_24G_OFFSET) /* Hz */
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/* Table 6-103. O-QPSK Transmitter Frontend Configuration */
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static uint8_t _TXCUTC_PARAMP(uint8_t chips)
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{
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switch (chips) {
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case BB_FCHIP100:
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return RF_PARAMP32U;
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case BB_FCHIP200:
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return RF_PARAMP16U;
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case BB_FCHIP1000:
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case BB_FCHIP2000:
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return RF_PARAMP4U;
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}
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return 0;
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}
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/* Table 6-103. O-QPSK Transmitter Frontend Configuration */
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static uint8_t _TXCUTC_LPFCUT(uint8_t chips)
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{
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switch (chips) {
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case BB_FCHIP100:
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case BB_FCHIP200:
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return RF_FLC400KHZ;
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case BB_FCHIP1000:
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case BB_FCHIP2000:
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return RF_FLC1000KHZ;
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}
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return 0;
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}
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/* Table 6-103. O-QPSK Transmitter Frontend Configuration */
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static uint8_t _TXDFE_SR(uint8_t chips)
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{
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switch (chips) {
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case BB_FCHIP100:
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return RF_SR_400K;
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case BB_FCHIP200:
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return RF_SR_800K;
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case BB_FCHIP1000:
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return RF_SR_4000K;
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case BB_FCHIP2000:
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return RF_SR_4000K;
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}
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return 0;
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}
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/* Table 6-103. O-QPSK Transmitter Frontend Configuration */
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static uint8_t _TXDFE_RCUT(uint8_t chips)
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{
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return (chips == BB_FCHIP2000 ? RF_RCUT_FS_BY_2 : RF_RCUT_FS_BY_2P6);
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}
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/* Table 6-105. O-QPSK Receiver Frontend Configuration (Filter Settings) */
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static uint8_t _RXBWC_BW(uint8_t chips)
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{
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switch (chips) {
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case BB_FCHIP100:
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return RF_BW160KHZ_IF250KHZ;
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case BB_FCHIP200:
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return RF_BW250KHZ_IF250KHZ;
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case BB_FCHIP1000:
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return RF_BW1000KHZ_IF1000KHZ;
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case BB_FCHIP2000:
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return RF_BW2000KHZ_IF2000KHZ;
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}
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return 0;
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}
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/* Table 6-105. O-QPSK Receiver Frontend Configuration (Filter Settings) */
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static uint8_t _RXDFE_SR(uint8_t chips)
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{
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switch (chips) {
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case BB_FCHIP100:
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return RF_SR_400K;
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case BB_FCHIP200:
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return RF_SR_800K;
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case BB_FCHIP1000:
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case BB_FCHIP2000:
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return RF_SR_4000K;
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}
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return 0;
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}
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/* Table 6-105. O-QPSK Receiver Frontend Configuration (Filter Settings) */
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static uint8_t _RXDFE_RCUT(uint8_t chips)
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{
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switch (chips) {
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case BB_FCHIP100:
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case BB_FCHIP200:
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return RF_RCUT_FS_BY_5P3;
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case BB_FCHIP1000:
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return RF_RCUT_FS_BY_8;
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case BB_FCHIP2000:
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return RF_RCUT_FS_BY_4;
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}
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return 0;
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}
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/* Table 6-106. O-QPSK Receiver Frontend Configuration (AGC Settings) */
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static inline uint8_t _AGCC(uint8_t chips)
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{
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if (chips > BB_FCHIP200) {
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/* 32 samples */
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return (2 << AGCC_AVGS_SHIFT) | AGCC_EN_MASK;
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} else {
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return AGCC_EN_MASK;
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}
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}
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/* Table 6-100. MR-O-QPSK Modes */
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static uint32_t _get_bitrate(uint8_t chips, uint8_t mode)
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{
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switch (chips) {
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case BB_FCHIP100:
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return 6250 * (1 << mode);
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case BB_FCHIP200:
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return 12500 * (1 << mode);
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case BB_FCHIP1000:
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case BB_FCHIP2000:
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return mode ? 125000 * (1 << (mode - 1)) : 31250;
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}
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return 0;
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}
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static void _set_chips(at86rf215_t *dev, uint8_t chips)
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{
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/* enable direct modulation if the chip supports it */
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uint8_t direct_modulation;
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if (chips < BB_FCHIP1000 && at86rf215_reg_read(dev, RG_RF_VN) >= 3) {
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direct_modulation = TXDFE_DM_MASK;
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} else {
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direct_modulation = 0;
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}
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/* Set Receiver Bandwidth */
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at86rf215_reg_write(dev, dev->RF->RG_RXBWC, _RXBWC_BW(chips));
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/* Set fS; fCUT for RX */
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at86rf215_reg_write(dev, dev->RF->RG_RXDFE, _RXDFE_SR(chips)
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| _RXDFE_RCUT(chips));
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/* Set Power Amplifier Ramp Time; fLPCUT */
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at86rf215_reg_write(dev, dev->RF->RG_TXCUTC, _TXCUTC_PARAMP(chips)
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| _TXCUTC_LPFCUT(chips));
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/* Set fS; fCUT for TX */
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at86rf215_reg_write(dev, dev->RF->RG_TXDFE, _TXDFE_SR(chips)
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| _TXDFE_RCUT(chips)
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| direct_modulation);
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/* set receiver gain target according to data sheet, p125 */
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at86rf215_reg_write(dev, dev->RF->RG_AGCS, 3 << AGCS_TGT_SHIFT);
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at86rf215_reg_write(dev, dev->RF->RG_AGCC, _AGCC(chips));
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/* use RC-0.8 shaping */
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at86rf215_reg_write(dev, dev->BBC->RG_OQPSKC0, chips | direct_modulation);
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}
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static void _set_legacy(at86rf215_t *dev, bool high_rate)
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{
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uint8_t chips;
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/* enable/disable legacy high data rate, only use SFD_1 */
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if (high_rate) {
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at86rf215_reg_write(dev, dev->BBC->RG_OQPSKC3, OQPSKC3_HRLEG_MASK);
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} else {
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at86rf215_reg_write(dev, dev->BBC->RG_OQPSKC3, 0);
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}
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if (is_subGHz(dev)) {
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chips = BB_FCHIP1000;
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} else {
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chips = BB_FCHIP2000;
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}
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_set_chips(dev, chips);
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at86rf215_reg_write(dev, dev->BBC->RG_OQPSKPHRTX, AT86RF215_OQPSK_MODE_LEGACY);
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at86rf215_reg_write(dev, dev->BBC->RG_OQPSKC2,
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RXM_LEGACY_OQPSK /* receive mode, legacy O-QPSK */
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| OQPSKC2_FCSTLEG_MASK /* 16 bit frame checksum */
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| OQPSKC2_ENPROP_MASK); /* enable RX of proprietary modes */
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}
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static void _set_ack_timeout(at86rf215_t *dev, uint8_t chips, uint8_t mode)
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{
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dev->ack_timeout_usec = AT86RF215_ACK_PERIOD_IN_BITS * US_PER_SEC / _get_bitrate(chips, mode);
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DEBUG("[%s] ACK timeout: %"PRIu32" µs\n", "O-QPSK", dev->ack_timeout_usec);
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}
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static void _set_csma_backoff_period(at86rf215_t *dev, uint8_t chips, uint8_t mode)
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{
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dev->csma_backoff_period = AT86RF215_BACKOFF_PERIOD_IN_BITS * US_PER_SEC / _get_bitrate(chips, mode);
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DEBUG("[%s] CSMA BACKOFF: %"PRIu32" µs\n", "O-QPSK", dev->csma_backoff_period);
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}
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void _end_configure_OQPSK(at86rf215_t *dev)
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{
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/* set channel spacing with 25 kHz resolution */
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if (is_subGHz(dev)) {
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at86rf215_reg_write(dev, dev->RF->RG_CS, QPSK_CHANNEL_SPACING_SUBGHZ / 25);
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at86rf215_reg_write16(dev, dev->RF->RG_CCF0L, QPSK_CENTER_FREQUENCY_SUBGHZ / 25);
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} else {
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at86rf215_reg_write(dev, dev->RF->RG_CS, QPSK_CHANNEL_SPACING_24GHZ / 25);
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at86rf215_reg_write16(dev, dev->RF->RG_CCF0L, QPSK_CENTER_FREQUENCY_24GHZ / 25);
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}
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/* lowest preamble detection sensitivity, enable receiver override */
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at86rf215_reg_write(dev, dev->BBC->RG_OQPSKC1, OQPSKC1_RXO_MASK | OQPSKC1_RXOLEG_MASK);
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/* make sure the channel config is still valid */
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dev->num_chans = is_subGHz(dev) ? 1 : 16;
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dev->netdev.chan = at86rf215_chan_valid(dev, dev->netdev.chan);
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at86rf215_reg_write16(dev, dev->RF->RG_CNL, dev->netdev.chan);
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at86rf215_enable_radio(dev, BB_MROQPSK);
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}
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int at86rf215_configure_legacy_OQPSK(at86rf215_t *dev, bool high_rate)
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{
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/* select 'mode' that would result in the approprate MR-O-QPSK data rate */
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uint8_t mode = high_rate ? 3 : 2;
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uint8_t chips = is_subGHz(dev) ? BB_FCHIP1000 : BB_FCHIP2000;
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at86rf215_await_state_end(dev, RF_STATE_TX);
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/* disable radio */
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at86rf215_reg_write(dev, dev->BBC->RG_PC, 0);
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_set_legacy(dev, high_rate);
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_set_csma_backoff_period(dev, chips, mode);
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_set_ack_timeout(dev, chips, mode);
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_end_configure_OQPSK(dev);
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return 0;
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}
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