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2b37d369a0
Implements workaround 1 (use __DSB()) proposed in the stm32 errata It was possible to lose data when you configure a peripheral right after enabling its clock
100 lines
2.4 KiB
C
100 lines
2.4 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Shared CPU specific function for the STM32 CPU family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "periph_conf.h"
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#include "periph_cpu_common.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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uint32_t periph_apb_clk(uint8_t bus)
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{
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if (bus == APB1) {
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return CLOCK_APB1;
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}
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else {
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return CLOCK_APB2;
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}
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}
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void periph_clk_en(bus_t bus, uint32_t mask)
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{
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switch (bus) {
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case APB1:
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RCC->APB1ENR |= mask;
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break;
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case APB2:
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RCC->APB2ENR |= mask;
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break;
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
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|| defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
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case AHB:
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RCC->AHBENR |= mask;
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break;
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#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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case AHB1:
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RCC->AHB1ENR |= mask;
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break;
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case AHB2:
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RCC->AHB2ENR |= mask;
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break;
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case AHB3:
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RCC->AHB3ENR |= mask;
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break;
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#endif
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default:
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DEBUG("unsupported bus %d\n", (int)bus);
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break;
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}
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/* stm32xx-errata: Delay after a RCC peripheral clock enable */
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__DSB();
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}
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void periph_clk_dis(bus_t bus, uint32_t mask)
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{
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switch (bus) {
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case APB1:
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RCC->APB1ENR &= ~(mask);
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break;
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case APB2:
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RCC->APB2ENR &= ~(mask);
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break;
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
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|| defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
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case AHB:
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RCC->AHBENR &= ~(mask);
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break;
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#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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case AHB1:
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RCC->AHB1ENR &= ~(mask);
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break;
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case AHB2:
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RCC->AHB2ENR &= ~(mask);
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break;
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case AHB3:
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RCC->AHB3ENR &= ~(mask);
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break;
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#endif
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default:
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DEBUG("unsupported bus %d\n", (int)bus);
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break;
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}
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}
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