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https://github.com/RIOT-OS/RIOT.git
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186 lines
9.0 KiB
C
186 lines
9.0 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_cc2538_gptimer CC2538 General Purpose Timer
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* @ingroup cpu_cc2538_regs
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* @{
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*
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* @file
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* @brief CC2538 General Purpose Timer (GPTIMER) driver
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*
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* @author Ian Martin <ian@locicontrols.com>
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*/
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#ifndef GPTIMER_H
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#define GPTIMER_H
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#include <stdint.h>
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#include "cc2538.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define GPTIMER_NUMOF 4 /**< The CC2538 has four general-purpose timer units. */
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#define NUM_CHANNELS_PER_GPTIMER 2 /**< Each G.P. timer unit has two channels: A and B. */
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enum {
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GPTIMER_ONE_SHOT_MODE = 1, /**< GPTIMER one-shot mode */
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GPTIMER_PERIODIC_MODE = 2, /**< GPTIMER periodic mode */
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GPTIMER_CAPTURE_MODE = 3, /**< GPTIMER capture mode */
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};
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enum {
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GPTMCFG_32_BIT_TIMER = 0, /**< 32-bit timer configuration */
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GPTMCFG_32_BIT_REAL_TIME_CLOCK = 1, /**< 32-bit real-time clock */
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GPTMCFG_16_BIT_TIMER = 4, /**< 16-bit timer configuration */
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};
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/**
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* @brief GPTIMER component registers
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*/
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typedef struct {
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cc2538_reg_t CFG; /**< GPTIMER Configuration */
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/**
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* @brief Timer A
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*/
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union {
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cc2538_reg_t TAMR; /**< GPTIMER Timer A mode */
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struct {
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cc2538_reg_t TAMR2 : 2; /**< GPTM Timer A mode */
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cc2538_reg_t TACMR : 1; /**< GPTM Timer A capture mode */
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cc2538_reg_t TAAMS : 1; /**< GPTM Timer A alternate mode */
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cc2538_reg_t TACDIR : 1; /**< GPTM Timer A count direction */
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cc2538_reg_t TAMIE : 1; /**< GPTM Timer A match interrupt enable */
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cc2538_reg_t TAWOT : 1; /**< GPTM Timer A wait-on-trigger */
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cc2538_reg_t TASNAPS : 1; /**< GPTM Timer A snap shot mode */
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cc2538_reg_t TAILD : 1; /**< GPTM Timer A interval load write */
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cc2538_reg_t TAPWMIE : 1; /**< GPTM Timer A PWM interrupt enable */
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cc2538_reg_t TAMRSU : 1; /**< Timer A match register update mode */
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cc2538_reg_t TAPLO : 1; /**< Legacy PWM operation */
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cc2538_reg_t RESERVED5 : 20; /**< Reserved bits */
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} TAMRbits;
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} cc2538_gptimer_tamr;
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/**
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* @brief Timer B
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*/
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union {
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cc2538_reg_t TBMR; /**< GPTIMER Timer B mode */
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struct {
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cc2538_reg_t TBMR2 : 2; /**< GPTM Timer B mode */
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cc2538_reg_t TBCMR : 1; /**< GPTM Timer B capture mode */
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cc2538_reg_t TBAMS : 1; /**< GPTM Timer B alternate mode */
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cc2538_reg_t TBCDIR : 1; /**< GPTM Timer B count direction */
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cc2538_reg_t TBMIE : 1; /**< GPTM Timer B match interrupt enable */
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cc2538_reg_t TBWOT : 1; /**< GPTM Timer B wait-on-trigger */
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cc2538_reg_t TBSNAPS : 1; /**< GPTM Timer B snap shot mode */
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cc2538_reg_t TBILD : 1; /**< GPTM Timer B interval load write */
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cc2538_reg_t TBPWMIE : 1; /**< GPTM Timer B PWM interrupt enable */
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cc2538_reg_t TBMRSU : 1; /**< Timer B match register update mode */
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cc2538_reg_t TBPLO : 1; /**< Legacy PWM operation */
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cc2538_reg_t RESERVED6 : 20; /**< Reserved bits */
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} TBMRbits;
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} cc2538_gptimer_tbmr;
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/**
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* @brief Timer Control
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*/
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union {
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cc2538_reg_t CTL; /**< GPTIMER Control */
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struct {
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cc2538_reg_t TAEN : 1; /**< GPTM Timer A enable */
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cc2538_reg_t TASTALL : 1; /**< GPTM Timer A stall enable */
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cc2538_reg_t TAEVENT : 1; /**< GPTM Timer A event mode */
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cc2538_reg_t RESERVED1 : 1; /**< Reserved bits */
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cc2538_reg_t TAOTE : 1; /**< GPTM Timer A PWM output trigger enable */
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cc2538_reg_t TAPWML : 1; /**< GPTM Timer A PWM output level */
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cc2538_reg_t RESERVED2 : 1; /**< Reserved bits */
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cc2538_reg_t TBEN : 1; /**< GPTM Timer B enable */
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cc2538_reg_t TBSTALL : 1; /**< GPTM Timer B stall enable */
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cc2538_reg_t TBEVENT : 1; /**< GPTM Timer B event mode */
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cc2538_reg_t RESERVED3 : 1; /**< Reserved bits */
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cc2538_reg_t TBOTE : 1; /**< GPTM Timer B PWM output trigger enable */
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cc2538_reg_t TBPWML : 1; /**< GPTM Timer B PWM output level */
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cc2538_reg_t RESERVED4 : 17; /**< Reserved bits */
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} CTLbits;
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} cc2538_gptimer_ctl;
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cc2538_reg_t SYNC; /**< GPTIMER Synchronize */
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cc2538_reg_t RESERVED2; /**< Reserved word */
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/**
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* @brief Interrupt mask control
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*/
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union {
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cc2538_reg_t IMR; /**< GPTIMER Interrupt Mask */
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struct {
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cc2538_reg_t TATOIM : 1; /**< GPTM Timer A time-out interrupt mask */
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cc2538_reg_t CAMIM : 1; /**< GPTM Timer A capture match interrupt mask */
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cc2538_reg_t CAEIM : 1; /**< GPTM Timer A capture event interrupt mask */
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cc2538_reg_t RESERVED1 : 1; /**< Reserved bits */
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cc2538_reg_t TAMIM : 1; /**< GPTM Timer A match interrupt mask */
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cc2538_reg_t RESERVED2 : 3; /**< Reserved bits */
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cc2538_reg_t TBTOIM : 1; /**< GPTM Timer B time-out interrupt mask */
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cc2538_reg_t CBMIM : 1; /**< GPTM Timer B capture match interrupt mask */
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cc2538_reg_t CBEIM : 1; /**< GPTM Timer B capture event interrupt mask */
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cc2538_reg_t TBMIM : 1; /**< GPTM Timer B match interrupt mask */
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cc2538_reg_t RESERVED3 : 20; /**< Reserved bits */
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} IMRbits;
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} cc2538_gptimer_imr;
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cc2538_reg_t RIS; /**< GPTIMER Raw Interrupt Status */
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cc2538_reg_t MIS; /**< GPTIMER Masked Interrupt Status */
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cc2538_reg_t ICR; /**< GPTIMER Interrupt Clear */
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cc2538_reg_t TAILR; /**< GPTIMER Timer A Interval Load */
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cc2538_reg_t TBILR; /**< GPTIMER Timer B Interval Load */
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cc2538_reg_t TAMATCHR; /**< GPTIMER Timer A Match */
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cc2538_reg_t TBMATCHR; /**< GPTIMER Timer B Match */
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cc2538_reg_t TAPR; /**< GPTIMER Timer A Prescale Register */
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cc2538_reg_t TBPR; /**< GPTIMER Timer B Prescale Register */
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cc2538_reg_t TAPMR; /**< GPTIMER Timer A Prescale Match Register */
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cc2538_reg_t TBPMR; /**< GPTIMER Timer B Prescale Match Register */
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cc2538_reg_t TAR; /**< GPTIMER Timer A */
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cc2538_reg_t TBR; /**< GPTIMER Timer B */
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cc2538_reg_t TAV; /**< GPTIMER Timer A Value */
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cc2538_reg_t TBV; /**< GPTIMER Timer B Value */
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cc2538_reg_t RESERVED3; /**< Reserved word */
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cc2538_reg_t TAPS; /**< GPTIMER Timer A Prescale Snapshot */
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cc2538_reg_t TBPS; /**< GPTIMER Timer B Prescale Snapshot */
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cc2538_reg_t TAPV; /**< GPTIMER Timer A Prescale Value */
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cc2538_reg_t TBPV; /**< GPTIMER Timer B Prescale Value */
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cc2538_reg_t RESERVED[981]; /**< Reserved */
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cc2538_reg_t PP; /**< GPTIMER Peripheral Properties */
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cc2538_reg_t RESERVED4[15]; /**< Reserved */
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} cc2538_gptimer_t;
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#define GPTIMER0 ( (cc2538_gptimer_t*)0x40030000 ) /**< GPTIMER0 Instance */
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#define GPTIMER1 ( (cc2538_gptimer_t*)0x40031000 ) /**< GPTIMER1 Instance */
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#define GPTIMER2 ( (cc2538_gptimer_t*)0x40032000 ) /**< GPTIMER2 Instance */
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#define GPTIMER3 ( (cc2538_gptimer_t*)0x40033000 ) /**< GPTIMER3 Instance */
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void isr_timer0_chan0(void); /**< RIOT Timer 0 Channel 0 Interrupt Service Routine */
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void isr_timer0_chan1(void); /**< RIOT Timer 0 Channel 1 Interrupt Service Routine */
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void isr_timer1_chan0(void); /**< RIOT Timer 1 Channel 0 Interrupt Service Routine */
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void isr_timer1_chan1(void); /**< RIOT Timer 1 Channel 1 Interrupt Service Routine */
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void isr_timer2_chan0(void); /**< RIOT Timer 2 Channel 0 Interrupt Service Routine */
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void isr_timer2_chan1(void); /**< RIOT Timer 2 Channel 1 Interrupt Service Routine */
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void isr_timer3_chan0(void); /**< RIOT Timer 3 Channel 0 Interrupt Service Routine */
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void isr_timer3_chan1(void); /**< RIOT Timer 3 Channel 1 Interrupt Service Routine */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* GPTIMER_H */
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/* @} */
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