mirror of
https://github.com/RIOT-OS/RIOT.git
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358 lines
9.3 KiB
C
358 lines
9.3 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_samr21-xpro
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* @{
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*
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* @file
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* @brief Configuration of CPU peripherals for the Atmel SAM R21 Xplained
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* Pro board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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#include <stdint.h>
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief External oscillator and clock configuration
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*
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* For selection of the used CORECLOCK, we have implemented two choices:
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*
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* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
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* - usage of the internal 8MHz oscillator directly, divided by N if needed
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*
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*
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* The PLL option allows for the usage of a wider frequency range and a more
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* stable clock with less jitter. This is why we use this option as default.
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*
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* The target frequency is computed from the PLL multiplier and the PLL divisor.
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* Use the following formula to compute your values:
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*
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* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
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*
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* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
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* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
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*
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*
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* The internal Oscillator used directly can lead to a slightly better power
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* efficiency to the cost of a less stable clock. Use this option when you know
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* what you are doing! The actual core frequency is adjusted as follows:
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*
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* CORECLOCK = 8MHz / DIV
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*
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* NOTE: A core clock frequency below 1MHz is not recommended
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
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#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
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/* generate the actual used core clock frequency */
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#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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/* generate the actual core clock frequency */
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#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
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#endif
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/** @} */
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TC3->COUNT16
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#define TIMER_0_CHANNELS 2
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_ISR isr_tc3
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/* Timer 1 configuration */
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#define TIMER_1_DEV TC4->COUNT32
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#define TIMER_1_CHANNELS 2
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_ISR isr_tc4
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV SERCOM0->USART
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#define UART_0_IRQ SERCOM0_IRQn
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#define UART_0_ISR isr_sercom0
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/* UART 0 pin configuration */
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#define UART_0_PORT (PORT->Group[0])
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#define UART_0_TX_PIN (4)
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#define UART_0_RX_PIN (5)
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#define UART_0_PINS (PORT_PA04 | PORT_PA05)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (PWM_0_EN + PWM_1_EN)
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#define PWM_0_EN 1
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#define PWM_1_EN 1
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#define PWM_MAX_CHANNELS 2
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/* for compatibility with test application */
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#define PWM_0_CHANNELS PWM_MAX_CHANNELS
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#define PWM_1_CHANNELS PWM_MAX_CHANNELS
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/**
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* @brief PWM channel configuration data structure
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*
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* TODO: this should be moved into the CPU folder
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*/
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typedef struct {
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PortGroup *port; /**< GPIO port */
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uint8_t pin; /**< GPIO pin */
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uint8_t fnct; /**< pin function multiplex value */
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uint8_t chan; /**< TCC channel to use */
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} pwm_conf_chan_t;
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/**
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* @brief PWM device configuration data structure
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*
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* TODO: this should be moved into the CPU folder
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*/
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typedef struct {
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Tcc *dev; /*< TCC device to use */
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pwm_conf_chan_t chan[2]; /**< channel configuration */
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} pwm_conf_t;
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/* PWM device configuration */
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#if PWM_NUMOF
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static const pwm_conf_t pwm_config[] = {
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#if PWM_0_EN
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{TCC1, {
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/* port , pin, AF, chan */
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{(PortGroup *)0x41004400, 6, 4, 0},
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{(PortGroup *)0x41004400, 7, 4, 1}
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}},
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#endif
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#if PWM_1_EN
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{TCC0, {
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/* port , pin, AF, chan */
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{(PortGroup *)0x41004400, 18, 5, 2},
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{(PortGroup *)0x41004400, 19, 5, 3}
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}},
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#endif
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};
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#endif
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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/* SPI0 */
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#define SPI_0_DEV SERCOM4->SPI
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#define SPI_IRQ_0 SERCOM4_IRQn
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#define SPI_0_DOPO (1)
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#define SPI_0_DIPO (0)
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#define SPI_0_SCLK_DEV PORT->Group[2]
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#define SPI_0_SCLK_PIN (18)
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#define SPI_0_MISO_DEV PORT->Group[2]
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#define SPI_0_MISO_PIN (19)
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#define SPI_0_MOSI_DEV PORT->Group[1]
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#define SPI_0_MOSI_PIN (30)
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/* SPI1 */
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#define SPI_1_DEV SERCOM5->SPI
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#define SPI_IRQ_1 SERCOM5_IRQn
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#define SPI_1_DOPO (1)
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#define SPI_1_DIPO (2)
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#define SPI_1_SCLK_DEV PORT->Group[1]
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#define SPI_1_SCLK_PIN (23)
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#define SPI_1_MISO_DEV PORT->Group[1]
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#define SPI_1_MISO_PIN (02)
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#define SPI_1_MOSI_DEV PORT->Group[1]
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#define SPI_1_MOSI_PIN (22)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_1_EN 0
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#define I2C_2_EN 0
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#define I2C_3_EN 0
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#define I2C_IRQ_PRIO 1
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#define I2C_0_DEV SERCOM3->I2CM
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#define I2C_0_IRQ SERCOM3_IRQn
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#define I2C_0_ISR isr_sercom3
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/* I2C 0 pin configuration */
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#define I2C_0_PORT (PORT->Group[0])
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#define I2C_SDA PIN_PA16
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#define I2C_SCL PIN_PA17
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#define I2C_0_PINS (PORT_PA16 | PORT_PA17)
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define RANDOM_NUMOF (0U)
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/** @} */
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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#define RTC_DEV RTC->MODE2
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/** @} */
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/**
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* @name RTT configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTT_DEV RTC->MODE0
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#define RTT_IRQ RTC_IRQn
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#define RTT_IRQ_PRIO 10
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#define RTT_ISR isr_rtc
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
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#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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*/
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#define GPIO_NUMOF (9U)
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
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/*4-7 -> internal */
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#define GPIO_4_EN 1
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#define GPIO_5_EN 1
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#define GPIO_6_EN 1
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#define GPIO_7_EN 1
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#define GPIO_8_EN 1
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#define GPIO_9_EN 0
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#define GPIO_10_EN 0
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#define GPIO_11_EN 0
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#define GPIO_12_EN 0
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#define GPIO_13_EN 0
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#define GPIO_14_EN 0
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#define GPIO_15_EN 0
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#define GPIO_NO_EXTINT (18)
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/* GPIO channel 0 config */
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#define GPIO_0_DEV PORT->Group[0]
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#define GPIO_0_PIN (13)
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#define GPIO_0_EXTINT (13)
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/* GPIO channel 1 config */
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#define GPIO_1_DEV PORT->Group[0]
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#define GPIO_1_PIN (28)
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#define GPIO_1_EXTINT (8)
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/* GPIO channel 2 config */
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#define GPIO_2_DEV PORT->Group[0]
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#define GPIO_2_PIN (15)
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#define GPIO_2_EXTINT (15)
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/* GPIO channel 3 config */
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#define GPIO_3_DEV PORT->Group[1]
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#define GPIO_3_PIN (3)
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#define GPIO_3_EXTINT (3)
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/* GPIO 4-7 Internal radio pins*/
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/* GPIO channel 4 config radio CS*/
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#define GPIO_4_DEV PORT->Group[1]
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#define GPIO_4_PIN (31)
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#define GPIO_4_EXTINT GPIO_NO_EXTINT
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/* GPIO channel 5 config radio IRQ0*/
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#define GPIO_5_DEV PORT->Group[1]
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#define GPIO_5_PIN (0)
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#define GPIO_5_EXTINT (0)
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/* GPIO channel 6 config radio reset*/
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#define GPIO_6_DEV PORT->Group[1]
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#define GPIO_6_PIN (15)
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#define GPIO_6_EXTINT GPIO_NO_EXTINT
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/* GPIO channel 7 config radio sleep*/
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#define GPIO_7_DEV PORT->Group[0]
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#define GPIO_7_PIN (20)
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#define GPIO_7_EXTINT GPIO_NO_EXTINT
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/* GPIO channel 8 config */
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#define GPIO_8_DEV PORT->Group[0]
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#define GPIO_8_PIN (27)
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#define GPIO_8_EXTINT GPIO_NO_EXTINT
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/* GPIO channel 9 config */
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#define GPIO_9_DEV
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#define GPIO_9_PIN
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#define GPIO_9_EXTINT
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/* GPIO channel 10 config */
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#define GPIO_10_DEV
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#define GPIO_10_PIN
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#define GPIO_10_EXTINT
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/* GPIO channel 11 config */
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#define GPIO_11_DEV
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#define GPIO_11_PIN
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#define GPIO_11_EXTINT
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/* GPIO channel 12 config */
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#define GPIO_12_PIN
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#define GPIO_12_EXTINT
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/* GPIO channel 13 config */
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#define GPIO_13_PIN
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#define GPIO_13_EXTINT
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/* GPIO channel 14 config */
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#define GPIO_14_PIN
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#define GPIO_14_EXTINT
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/* GPIO channel 15 config */
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#define GPIO_15_PIN
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#define GPIO_15_EXTINT
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PERIPH_CONF_H */
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/** @} */
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