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104 lines
2.2 KiB
C
104 lines
2.2 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_adc
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* @{
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*
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* @file
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* @brief Low-level ADC driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/adc.h"
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/**
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* @brief Allocate lock for the ADC device
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*
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* All STM32F0 & STM32G0 CPUs we support so far only come with a single ADC device.
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*/
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static mutex_t lock = MUTEX_INIT;
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static inline void prep(void)
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{
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mutex_lock(&lock);
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#ifdef RCC_APB2ENR_ADCEN
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periph_clk_en(APB2, RCC_APB2ENR_ADCEN);
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#endif
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#ifdef RCC_APBENR2_ADCEN
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periph_clk_en(APB12, RCC_APBENR2_ADCEN);
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#endif
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}
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static inline void done(void)
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{
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#ifdef RCC_APB2ENR_ADCEN
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periph_clk_dis(APB2, RCC_APB2ENR_ADCEN);
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#endif
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#ifdef RCC_APBENR2_ADCEN
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periph_clk_dis(APB12, RCC_APBENR2_ADCEN);
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#endif
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mutex_unlock(&lock);
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}
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int adc_init(adc_t line)
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{
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/* make sure the given line is valid */
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if (line >= ADC_NUMOF) {
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return -1;
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}
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/* lock and power on the device */
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prep();
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/* configure the pin */
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gpio_init_analog(adc_config[line].pin);
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/* reset configuration */
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ADC1->CFGR2 = 0;
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/* enable device */
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ADC1->CR = ADC_CR_ADEN;
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/* configure sampling time to save value */
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ADC1->SMPR = 0x3; /* 28.5 ADC clock cycles */
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/* power off an release device for now */
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done();
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return 0;
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}
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int32_t adc_sample(adc_t line, adc_res_t res)
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{
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int sample;
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/* check if resolution is applicable */
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if (res > 0xf0) {
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return -1;
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}
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/* lock and power on the ADC device */
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prep();
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/* set resolution and channel */
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ADC1->CFGR1 = res;
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ADC1->CHSELR = (1 << adc_config[line].chan);
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/* start conversion and wait for results */
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ADC1->CR |= ADC_CR_ADSTART;
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while (!(ADC1->ISR & ADC_ISR_EOC)) {}
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/* read result */
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sample = (int)ADC1->DR;
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/* unlock and power off device again */
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done();
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return sample;
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}
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