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209 lines
10 KiB
C
209 lines
10 KiB
C
/*
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* Copyright 2008, Freie Universitaet Berlin (FUB). All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef CC1100_INTERNAL_H
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#define CC1100_INTERNAL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @ingroup dev_cc110x_legacy_csma
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* @{
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*/
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/**
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* @file
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* @internal
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* @brief TI Chipcon CC110x internal hardware constants
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*
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* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
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* @author Heiko Will <hwill@inf.fu-berlin.de>
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* @version $Revision: 1231 $
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*
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* @note $Id: cc1100-internal.h 1231 2009-08-20 08:31:32Z baar $
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*/
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#define FIXED_PKTLEN (0x00) ///< Fixed length packets, length configured in PKTLEN register.
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#define VARIABLE_PKTLEN (0x01) ///< Variable length packets, packet length configured by the first
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///< byte after synch word.
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/**
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* @name Bitmasks for reading out status register values
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* @{
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*/
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/**
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* @brief Bitmask (=10000000) for reading CRC_OK.
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*
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* If CRC_OK == 1: CRC for received data OK (or CRC disabled).
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* If CRC_OK == 0: CRC error in received data.
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*/
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#define CRC_OK (0x80)
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/**
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* @brief Bitmask (=01111111) for reading LQI_EST.
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*
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* The Link Quality Indicator estimates how easily a received signal can be demodulated.
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*/
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#define LQI_EST (0x7F)
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#define I_RSSI (0x00) ///< Index 0 contains RSSI information (from optionally appended packet status bytes).
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#define I_LQI (0x01) ///< Index 1 contains LQI & CRC_OK information (from optionally appended packet status bytes).
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#define MARC_STATE (0x1F) ///< Bitmask (=00011111) for reading MARC_STATE in MARCSTATE status register.
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#define CS (0x40) ///< Bitmask (=01000000) for reading CS (Carrier Sense) in PKTSTATUS status register.
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#define PQT_REACHED (0x20) ///< Bitmask (=00100000) for reading PQT_REACHED (Preamble Quality reached) in PKTSTATUS status register.
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#define CCA (0x10) ///< Bitmask (=00010000) for reading CCA (clear channel assessment) in PKTSTATUS status register.
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#define SFD (0x08) ///< Bitmask (=00001000) for reading SFD (Sync word found) in PKTSTATUS status register.
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#define GDO2 (0x04) ///< Bitmask (=00000100) for reading GDO2 (current value on GDO2 pin) in PKTSTATUS status register.
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#define GDO1 (0x02) ///< Bitmask (=00000010) for reading GDO1 (current value on GDO1 pin) in PKTSTATUS status register.
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#define GDO0 (0x01) ///< Bitmask (=00000001) for reading GDO0 (current value on GDO0 pin) in PKTSTATUS status register.
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#define TXFIFO_UNDERFLOW (0x80) ///< Bitmask (=10000000) for reading TXFIFO_UNDERFLOW in TXBYTES status register.
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#define BYTES_IN_TXFIFO (0x7F) ///< Bitmask (=01111111) for reading NUM_TXBYTES in TXBYTES status register.
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#define RXFIFO_OVERFLOW (0x80) ///< Bitmask (=10000000) for reading RXFIFO_OVERFLOW in RXBYTES status register.
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#define BYTES_IN_RXFIFO (0x7F) ///< Bitmask (=01111111) for reading NUM_RXBYTES in RXBYTES status register.
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/** @} */
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/**
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* @name Bitmasks for reading out configuration register values
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* @{
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*/
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#define PKT_LENGTH_CONFIG (0x03) ///< Bitmask (=00000011) for reading LENGTH_CONFIG in PKTCTRL0 configuration register.
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/** @} */
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/**
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* @name Definitions to support burst/single access
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* @{
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*/
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#define CC1100_WRITE_BURST (0x40) ///< Offset for burst write.
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#define CC1100_READ_SINGLE (0x80) ///< Offset for read single byte.
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#define CC1100_READ_BURST (0xC0) ///< Offset for read burst.
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#define CC1100_NOBYTE (0x00) ///< No command (for reading).
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/** @} */
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/**
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* @name Configuration Registers (47x)
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* @{
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*/
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#define CC1100_IOCFG2 (0x00) ///< GDO2 output pin configuration
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#define CC1100_IOCFG1 (0x01) ///< GDO1 output pin configuration
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#define CC1100_IOCFG0 (0x02) ///< GDO0 output pin configuration
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#define CC1100_FIFOTHR (0x03) ///< RX FIFO and TX FIFO thresholds
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#define CC1100_SYNC1 (0x04) ///< Sync word, high byte
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#define CC1100_SYNC0 (0x05) ///< Sync word, low byte
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#define CC1100_PKTLEN (0x06) ///< Packet length
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#define CC1100_PKTCTRL1 (0x07) ///< Packet automation control
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#define CC1100_PKTCTRL0 (0x08) ///< Packet automation control
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#define CC1100_ADDR (0x09) ///< Device address
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#define CC1100_CHANNR (0x0A) ///< Channel number
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#define CC1100_FSCTRL1 (0x0B) ///< Frequency synthesizer control
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#define CC1100_FSCTRL0 (0x0C) ///< Frequency synthesizer control
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#define CC1100_FREQ2 (0x0D) ///< Frequency control word, high byte
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#define CC1100_FREQ1 (0x0E) ///< Frequency control word, middle byte
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#define CC1100_FREQ0 (0x0F) ///< Frequency control word, low byte
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#define CC1100_MDMCFG4 (0x10) ///< Modem configuration
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#define CC1100_MDMCFG3 (0x11) ///< Modem configuration
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#define CC1100_MDMCFG2 (0x12) ///< Modem configuration
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#define CC1100_MDMCFG1 (0x13) ///< Modem configuration
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#define CC1100_MDMCFG0 (0x14) ///< Modem configuration
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#define CC1100_DEVIATN (0x15) ///< Modem deviation setting
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#define CC1100_MCSM2 (0x16) ///< Main Radio Control State Machine configuration
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#define CC1100_MCSM1 (0x17) ///< Main Radio Control State Machine configuration
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#define CC1100_MCSM0 (0x18) ///< Main Radio Control State Machine configuration
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#define CC1100_FOCCFG (0x19) ///< Frequency Offset Compensation configuration
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#define CC1100_BSCFG (0x1A) ///< Bit Synchronization configuration
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#define CC1100_AGCCTRL2 (0x1B) ///< AGC control
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#define CC1100_AGCCTRL1 (0x1C) ///< AGC control
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#define CC1100_AGCCTRL0 (0x1D) ///< AGC control
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#define CC1100_WOREVT1 (0x1E) ///< High byte Event 0 timeout
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#define CC1100_WOREVT0 (0x1F) ///< Low byte Event 0 timeout
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#define CC1100_WORCTRL (0x20) ///< Wake On Radio control
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#define CC1100_FREND1 (0x21) ///< Front end RX configuration
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#define CC1100_FREND0 (0x22) ///< Front end TX configuration
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#define CC1100_FSCAL3 (0x23) ///< Frequency synthesizer calibration
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#define CC1100_FSCAL2 (0x24) ///< Frequency synthesizer calibration
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#define CC1100_FSCAL1 (0x25) ///< Frequency synthesizer calibration
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#define CC1100_FSCAL0 (0x26) ///< Frequency synthesizer calibration
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#define CC1100_RCCTRL1 (0x27) ///< RC oscillator configuration
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#define CC1100_RCCTRL0 (0x28) ///< RC oscillator configuration
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#define CC1100_FSTEST (0x29) ///< Frequency synthesizer calibration control
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#define CC1100_PTEST (0x2A) ///< Production test
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#define CC1100_AGCTEST (0x2B) ///< AGC test
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#define CC1100_TEST2 (0x2C) ///< Various test settings
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#define CC1100_TEST1 (0x2D) ///< Various test settings
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#define CC1100_TEST0 (0x2E) ///< Various test settings
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/** @} */
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/**
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* @name Strobe commands (14x)
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* @{
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*/
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#define CC1100_SRES (0x30) ///< Reset chip.
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/**
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* @brief Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
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*
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* If in RX/TX: Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
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*/
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#define CC1100_SFSTXON (0x31)
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#define CC1100_SXOFF (0x32) ///< Turn off crystal oscillator.
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#define CC1100_SCAL (0x33) ///< Calibrate frequency synthesizer and turn it off (enables quick start).
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#define CC1100_SRX (0x34) ///< Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.
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/**
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* In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
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* If in RX state and CCA is enabled: Only go to TX if channel is clear.
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*/
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#define CC1100_STX (0x35)
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#define CC1100_SIDLE (0x36) ///< Exit RX / TX, turn off frequency synthesizer and exit WOR mode if applicable.
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#define CC1100_SAFC (0x37) ///< Perform AFC adjustment of the frequency synthesizer
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#define CC1100_SWOR (0x38) ///< Start automatic RX polling sequence (Wake-on-Radio)
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#define CC1100_SPWD (0x39) ///< Enter power down mode when CSn goes high.
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#define CC1100_SFRX (0x3A) ///< Flush the RX FIFO buffer (CC1100 should be in IDLE state).
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#define CC1100_SFTX (0x3B) ///< Flush the TX FIFO buffer (CC1100 should be in IDLE state).
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#define CC1100_SWORRST (0x3C) ///< Reset real time clock.
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#define CC1100_SNOP (0x3D) ///< No operation. May be used to pad strobe commands to two bytes for simpler software.
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/** @} */
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/**
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* @name Status registers (12x)
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* @{
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*/
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#define CC1100_PARTNUM (0x30) ///< Part number of CC1100.
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#define CC1100_VERSION (0x31) ///< Current version number.
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#define CC1100_FREQEST (0x32) ///< Frequency Offset Estimate.
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#define CC1100_LQI (0x33) ///< Demodulator estimate for Link Quality.
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#define CC1100_RSSI (0x34) ///< Received signal strength indication.
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#define CC1100_MARCSTATE (0x35) ///< Control state machine state.
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#define CC1100_WORTIME1 (0x36) ///< High byte of WOR timer.
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#define CC1100_WORTIME0 (0x37) ///< Low byte of WOR timer.
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#define CC1100_PKTSTATUS (0x38) ///< Current GDOx status and packet status.
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#define CC1100_VCO_VC_DAC (0x39) ///< Current setting from PLL calibration module.
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#define CC1100_TXBYTES (0x3A) ///< Underflow and number of bytes in the TX FIFO.
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#define CC1100_RXBYTES (0x3B) ///< Overflow and number of bytes in the RX FIFO.
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/** @} */
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/**
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* @name Multi byte registers
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* @{
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*/
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/**
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* @brief Register for eight user selected output power settings.
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*
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* 3-bit FREND0.PA_POWER value selects the PATABLE entry to use.
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*/
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#define CC1100_PATABLE (0x3E)
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#define CC1100_TXFIFO (0x3F) ///< TX FIFO: Write operations write to the TX FIFO (SB: +0x00; BURST: +0x40)
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#define CC1100_RXFIFO (0x3F) ///< RX FIFO: Read operations read from the RX FIFO (SB: +0x80; BURST: +0xC0)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif
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