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135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_cortexm_common ARM Cortex-M common
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* @ingroup cpu
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* @brief Common implementations and headers for Cortex-M family based
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* micro-controllers
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* @{
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*
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* @file
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* @brief Basic definitions for the Cortex-M common module
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*
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* When ever you want to do something hardware related, that is accessing MCUs
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* registers, just include this file. It will then make sure that the MCU
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* specific headers are included.
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*
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* @todo remove include irq.h once core was adjusted
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*/
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#ifndef CPU_H
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#define CPU_H
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#include <stdio.h>
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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#include "cpu_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Interrupt stack canary value
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*
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* @note 0xe7fe is the ARM Thumb machine code equivalent of asm("bl #-2\n") or
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* 'while (1);', i.e. an infinite loop.
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* @internal
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*/
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#define STACK_CANARY_WORD (0xE7FEE7FEu)
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/**
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* @brief All Cortex-m-based CPUs provide pm_set_lowest
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*
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* The pm_set_lowest is provided either by the pm_layered module if used, or
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* alternatively as fallback by the cortexm's own implementation.
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*/
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#define PROVIDES_PM_SET_LOWEST
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/**
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* @brief Initialization of the CPU
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*/
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void cpu_init(void);
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/**
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* @brief Initialize Cortex-M specific core parts of the CPU
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*/
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void cortexm_init(void);
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/**
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* @brief Prints the current content of the link register (lr)
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*/
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static inline void cpu_print_last_instruction(void)
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{
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uint32_t *lr_ptr;
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__asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
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printf("%p\n", (void*) lr_ptr);
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}
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/**
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* @brief Put the CPU into the 'wait for event' sleep mode
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*
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* This function is meant to be used for short periods of time, where it is not
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* feasible to switch to the idle thread and back.
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*/
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static inline void cortexm_sleep_until_event(void)
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{
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__WFE();
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}
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/**
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* @brief Put the CPU into (deep) sleep mode, using the `WFI` instruction
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*
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* @param[in] deep !=0 for deep sleep, 0 for light sleep
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*/
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static inline void cortexm_sleep(int deep)
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{
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if (deep) {
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SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);
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}
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else {
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SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
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}
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/* ensure that all memory accesses have completed and trigger sleeping */
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unsigned state = irq_disable();
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__DSB();
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__WFI();
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#if defined(CPU_MODEL_STM32L152RE)
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/* STM32L152RE crashes without this __NOP(). See #8518. */
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__NOP();
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#endif
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irq_restore(state);
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}
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/**
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* @brief Trigger a conditional context scheduler run / context switch
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*
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* This function is supposed to be called in the end of each ISR.
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*/
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static inline void cortexm_isr_end(void)
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{
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if (sched_context_switch_request) {
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thread_yield_higher();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_H */
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/** @} */
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