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371 lines
15 KiB
C
371 lines
15 KiB
C
/*
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* Copyright (C) 2023 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_stm32_periph_fmc STM32 FMC/FSMC peripheral driver
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* @ingroup cpu_stm32
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*
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* @{
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*
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* The `periph_fmc` module implements a driver for STM32 FMC/FSMC peripherals.
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* It supports
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* - NOR Flashes,
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* - PSRAMs/SRAMs,
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* - SDRAMs, and
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* - Display Controllers with MCU 8-/16-bit parallel interface.
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*
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* NAND Flashes are not yet supported.
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*
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* To use the FMC/FSMC, the `periph_fmc` module has to be enabled.
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* To keep required data structures and resulting code as small as possible,
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* a couple of pseudomodules are defined that have to be used in addition to
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* the `periph_fmc` module to enable supported features. These are:
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*
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* | Module | Feature |
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* |:-----------------------|:----------------------------------------|
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* | `periph_fmc_nor_sram` | enable NOR Flash and PSRAM/SRAM support |
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* | `periph_fmc_sdram` | enable SDRAM support |
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* | `periph_fmc_16bit` | enable 16-bit support |
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* | `periph_fmc_32bit` | enable 32-bit support |
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* \n
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*
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* The board has then to define
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* - the corresponding features according to the connected external device,
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* - the peripheral configuration of the FMC/FSMC of type @ref fmc_conf_t,
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* - the configuration of the FMC banks which describe the connected external
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* devices.
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*
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* As examples for such configurations, see @ref boards_stm32l496g-disco
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* (FMC with Display and SRAM) or @ref boards_stm32f429i-disc1 (FMC with SDRAM).
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*
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* To use the RAM connected to the FMC as heap, the board has also to define
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* @ref FMC_RAM_ADDR and @ref FMC_RAM_LEN.
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*
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* @file
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* @brief Specific FMC definitions for the STM32
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef PERIPH_CPU_FMC_H
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#define PERIPH_CPU_FMC_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph/cpu_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Number of data pins used
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*
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* The number of configured data pins depends on the memory with the maximum
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* data bus width. The maximum data bus width used has to be specified by the
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* pseudomodules `periph_fmc_16bit` and `periph_fmc_32bit`. 8 bit data bus
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* width is the default.
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*/
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#if MODULE_PERIPH_FMC_32BIT || DOXYGEN
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#define FMC_DATA_PIN_NUMOF (32)
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#elif MODULE_PERIPH_FMC_16BIT
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#define FMC_DATA_PIN_NUMOF (16)
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#else
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#define FMC_DATA_PIN_NUMOF (8)
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#endif
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/**
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* @brief Number of address pins used
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*
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* The number of configured address pins depends on the memory types used.
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* NORs, PSRAMs and SRAMs (module `periph_fmc_nor_sram`) use up to 26 address
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* signals A0...A25 if address/data multiplexing is not used. SDRAMs (module
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* `periph_fmc_sdram`) use only up to 13 address signals A0...A12.
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* NANDs (module `periph_fmc_sdram`) don't need separate address signals.
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* The type of used memories is specified by the corresponding pseudomodules.
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*/
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#if MODULE_PERIPH_FMC_NOR_SRAM || DOXYGEN
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#define FMC_ADDR_PIN_NUMOF (26)
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#elif MODULE_PERIPH_FMC_SDRAM
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#define FMC_ADDR_PIN_NUMOF (13)
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#else
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#define FMC_ADDR_PIN_NUMOF (0)
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#endif
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#if DOXYGEN
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/**
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* @brief Start address of the heap for the FMC RAM
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*
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* This variable has to be defined in `Makefile.include` of the board
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* definition to use the a RAM connected to the FMC as heap. It has to
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* correspond to the @ref fmc_bank_conf_t::address in FMC bank configuration.
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*
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* @note `FMC_RAM_ADDR` is not a macro and cannot be used in C code.
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* It is just defined for documentation purpose.
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*/
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#define FMC_RAM_ADDR 0x60000000
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/**
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* @brief Length of the heap for the FMC RAM
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*
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* This variable has to be defined in `Makefile.include` of the board
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* definition to use the a RAM connected to the FMC as heap. It has to
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* correspond to the @ref fmc_bank_conf_t::size in FMC bank configuration.
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* Since it is used in linker script, it has to be defined in kByte with
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* suffix `K`, e.g. `1024K`.
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*
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* @note `FMC_RAM_SIZE` is not a macro and cannot be used in C code.
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* It is just defined for documentation purpose.
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*/
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#define FMC_RAM_LEN 1024K
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#endif
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/**
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* @name Type declarations for NOR Flash, PSRAM and SRAM
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* @{
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*/
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/**
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* @brief Memory access modes for NOR/PSRAM/SRAM in extended mode
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*/
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typedef enum {
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FMC_MODE_A = 0, /**< Access mode A */
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FMC_MODE_B = 1, /**< Access mode B */
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FMC_MODE_C = 2, /**< Access mode C */
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FMC_MODE_D = 3, /**< Access mode D */
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} fmc_access_mode_t;
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/**
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* @brief Timing configuration for NOR/PSRAM/SRAM
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*
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* Used timing configuration parameters depend on used access mode. Please refer
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* the reference manual of the respective MCU for details.
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*/
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typedef struct {
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fmc_access_mode_t mode; /**< Access Mode used (only used if
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@ref fmc_nor_sram_bank_conf_t::ext_mode is true) */
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uint8_t clk_div; /**< Clock divide ratio, FMC_CLK = HCLK / (DIV + 1) */
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uint8_t addr_setup; /**< Address setup time [0..15], default 15 */
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uint8_t addr_hold; /**< Address hold time [0..15], default 15 */
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uint8_t data_setup; /**< Data setup time [0..15], default 15 */
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uint8_t data_latency; /**< Data latency for synchronous access [0..15],
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default 15 (only used in read timing) */
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uint8_t bus_turnaround; /**< Bus turnaround phase duration [0..15], default 15 */
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} fmc_nor_sram_timing_t;
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/**
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* @brief Bank configuration structure for NOR/PSRAM/SRAM
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*/
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typedef struct {
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uint8_t sub_bank; /**< Bank1 has 4 subbanks 1..4 */
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bool mux_enable; /**< Multiplexed address/data signals used
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(only valid for PSRAMs and NORs */
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bool wait_enable; /**< Wait signal used for synchronous
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access */
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bool ext_mode; /**< Extended mode used (separate read and
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write timings) */
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fmc_nor_sram_timing_t r_timing; /**< Read timings (also used for write if
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@ref fmc_nor_sram_bank_conf_t::ext_mode is false) */
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fmc_nor_sram_timing_t w_timing; /**< Write timings (only used if
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@ref fmc_nor_sram_bank_conf_t::ext_mode is true) */
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} fmc_nor_sram_bank_conf_t;
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/** @} */
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/**
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* @name Type declarations for SDRAMs
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* @{
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*/
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/**
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* @brief SDRAM Burst Length as an exponent of a power of two
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*/
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typedef enum {
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FMC_BURST_LENGTH_1 = 0, /* Burst length is 1 */
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FMC_BURST_LENGTH_2 = 1, /* Burst length is 2 */
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FMC_BURST_LENGTH_4 = 2, /* Burst length is 4 */
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FMC_BURST_LENGTH_8 = 3, /* Burst length is 8 */
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FMC_BURST_LENGTH_16 = 4, /* Burst length is 16 */
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FMC_BURST_LENGTH_32 = 5, /* Burst length is 32 */
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FMC_BURST_LENGTH_64 = 6, /* Burst length is 64 */
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FMC_BURST_LENGTH_FULL = 7, /* Burst length is full page */
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} fmc_bust_length_t;
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/**
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* @brief Timing configuration for SDRAM
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*/
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typedef struct {
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uint8_t row_to_col_delay; /**< Row to column delay in SDCLK clock
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cycles [1..16], delay between Activate
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and Read/Write command */
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uint8_t row_precharge; /**< Row precharge delay in SDCLK clock
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cycles [1..15], delay between Precharge
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and another command */
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uint8_t recovery_delay; /**< Recovery delay in SDCLK clock
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cycles [1..15], delay between Write and
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Precharge command */
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uint8_t row_cylce; /**< Row cycle delay in SDCLK clock
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cycles [1..15], delay between Refresh and
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Activate command */
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uint8_t self_refresh; /**< Self refresh time in SDCLK clock
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cycles [1..15] */
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uint8_t exit_self_refresh; /**< Exit self-refresh delay in SDCLK clock
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cycles [1..15], delay between Self-Refresh
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and Activate command */
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uint8_t load_mode_register; /**< Load Mode Register to Activate delay in
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SDCLK clock cycles [1..15], delay between
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Load Mode Register and Activate command */
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uint8_t refresh_period; /**< Refresh period in milliseconds */
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} fmc_sdram_timing_t;
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/**
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* @brief Bank configuration structure for SDRAM
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*/
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typedef struct {
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uint8_t clk_period; /**< CLK period [0,2,3] (0 - disabled, n * HCLK cycles) */
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uint8_t row_bits; /**< Number row address bits [11..13] */
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uint8_t col_bits; /**< Number column address bits [8..11]*/
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uint8_t cas_latency; /**< CAS latency in SDCLK clock cycles [1..3] */
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uint8_t read_delay; /**< Delay for reading data after CAS latency in HCLKs [0..2] */
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bool four_banks; /**< SDRAM has four internal banks */
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bool write_protect; /**< Write protection enabled */
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bool burst_read; /**< Burst read mode enabled */
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bool burst_write; /**< Burst write mode enabled */
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bool burst_interleaved; /**< Burst mode interleaved, otherwise sequential */
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fmc_bust_length_t burst_len; /**< Burst length as an exponent of a power of two */
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fmc_sdram_timing_t timing; /**< SDRAM Timing configuration */
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} fmc_sdram_bank_conf_t;
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/** @} */
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/**
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* @name Type declarations that are common for all memories
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* @{
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*/
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/**
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* @brief FMC GPIO configuration type
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*/
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typedef struct {
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gpio_t pin; /**< GPIO pin */
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gpio_af_t af; /**< Alternate function */
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} fmc_gpio_t;
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/**
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* @brief FMC peripheral configuration
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*
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* The GPIOs are defined depending on used memory type according to the
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* FMC pin definition in Table 12 of section 4 in the
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* [Datasheet for STM32F765xx, STM32F767xx, STM32F768Ax, STM32F769xx]
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* (https://www.st.com/resource/en/datasheet/stm32f767zi.pdf).
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* Which memory types are used is defined by the pseudomodules
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* `periph_fmc_nor_sram`, `periph_fmc_nand` and `periph_fmc_sdram`
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*
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* @note For easier handling the configuration structure does not take
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* multiplexed address/data bits into account.
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*/
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typedef struct {
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uint8_t bus; /**< AHB/APB bus */
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uint32_t rcc_mask; /**< Bit in clock enable register */
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fmc_gpio_t data[FMC_DATA_PIN_NUMOF]; /**< Data pins D0 ... */
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#if FMC_ADDR_PIN_NUMOF || DOXYGEN
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fmc_gpio_t addr[FMC_ADDR_PIN_NUMOF]; /**< Address pins A0 ... if any */
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#endif
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/* signals used by all kind of memories */
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fmc_gpio_t nbl0_pin; /**< NBL0 pin */
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fmc_gpio_t nbl1_pin; /**< NBL1 pin */
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fmc_gpio_t nbl2_pin; /**< NBL2 pin */
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fmc_gpio_t nbl3_pin; /**< NBL3 pin */
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fmc_gpio_t nwait_pin; /**< NWAIT pin */
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#if MODULE_PERIPH_FMC_NOR_SRAM
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/* NORs, PSRAMs, and SRAMs use CLK, NOE, NWE, NE, and NADV signals **/
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fmc_gpio_t clk_pin; /**< CLK pin */
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fmc_gpio_t noe_pin; /**< NOE pin (output enable / read enable) */
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fmc_gpio_t nwe_pin; /**< NWE pin (write enable) */
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fmc_gpio_t ne1_pin; /**< NE1 pin (subbank 1 enable) */
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fmc_gpio_t ne2_pin; /**< NE2 pin (subbank 2 enable) */
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fmc_gpio_t ne3_pin; /**< NE3 pin (subbank 3 enable) */
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fmc_gpio_t ne4_pin; /**< NE4 pin (subbank 4 enable) */
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fmc_gpio_t nadv_pin; /**< NADV pin (address valid) */
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#endif /* MODULE_PERIPH_FMC_NORSRAM */
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#if MODULE_PERIPH_FMC_SDRAM
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/* SDRAMs use BAx, CLK, RAS, CAS, WE, ... signals **/
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fmc_gpio_t ba0_pin; /**< BA0 pin */
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fmc_gpio_t ba1_pin; /**< BA1 pin */
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fmc_gpio_t sdclk_pin; /**< SDCLK pin */
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fmc_gpio_t sdnwe_pin; /**< SDWE pin */
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fmc_gpio_t sdnras_pin; /**< SDNRAS pin */
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fmc_gpio_t sdncas_pin; /**< SDNCAS pin */
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fmc_gpio_t sdcke0_pin; /**< SDCKE0 pin (SDRAM bank 5 clock enable) */
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fmc_gpio_t sdcke1_pin; /**< SDCKE1 pin (SDRAM bank 6 clock enable) */
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fmc_gpio_t sdne0_pin; /**< SDNE0 pin (SDRAM bank 5 enable) */
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fmc_gpio_t sdne1_pin; /**< SDNE1 pin (SDRAM bank 6 enable) */
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#endif /* MODULE_PERIPH_FMC_SDRAM */
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} fmc_conf_t;
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/**
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* @brief Memory banks
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*/
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typedef enum {
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FMC_BANK_1 = 1, /**< Bank 1 is always available and used for NOR, PSRAM, SRAM */
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#if defined(FMC_Bank2_3_R_BASE)
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FMC_BANK_2 = 2, /**< Bank2 is used for NAND if available */
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#endif
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#if defined(FMC_Bank2_3_R_BASE) || defined(FMC_Bank3_R_BASE)
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FMC_BANK_3 = 3, /**< Bank3 is used for NAND if available */
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#endif
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#if defined(FMC_Bank4_R_BASE)
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FMC_BANK_4 = 4, /**< Bank4 is used for PC Card if available */
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#endif
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#if defined(FMC_Bank5_6_R_BASE)
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FMC_BANK_5 = 5, /**< Bank5 is used for SDRAM if available */
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FMC_BANK_6 = 6, /**< Bank6 is used for SDRAM if available */
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#endif
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} fmc_bank_t;
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/**
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* @brief Memory types supported by the FMC controller
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*/
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typedef enum {
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FMC_SRAM = 0, /**< SRAM */
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FMC_PSRAM = 1, /**< PSRAM */
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FMC_NOR = 2, /**< NOR Flash */
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FMC_NAND = 3, /**< NAND Flash */
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FMC_SDRAM = 4, /**< SDRAM Controller used */
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} fmc_mem_type_t;
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/**
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* @brief Memory data bus widths
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*/
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typedef enum {
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FMC_BUS_WIDTH_8BIT = 0, /**< 8 bit data bus width */
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FMC_BUS_WIDTH_16BIT = 1, /**< 16 bit data bus width */
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FMC_BUS_WIDTH_32BIT = 2, /**< 32 bit data bus width */
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} fmc_bus_width_t;
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/**
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* @brief Bank configuration structure
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*/
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typedef struct {
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fmc_bank_t bank; /**< Bank1 .. Bank4/Bank6 (maximum) */
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fmc_mem_type_t mem_type; /**< Type of memory */
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fmc_bus_width_t data_width; /**< Data bus width */
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uint32_t address; /**< Address of the memory bank */
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uint32_t size; /**< Size in bytes of the memory bank */
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union {
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fmc_nor_sram_bank_conf_t nor_sram; /* Configuration in case of NOR/PSRAM/SRAM */
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fmc_sdram_bank_conf_t sdram; /* Configuration in case of SDRAM */
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};
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} fmc_bank_conf_t;
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typedef uint8_t fmc_bank_id_t; /**< FMC bank identifier */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_FMC_H */
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/** @} */
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