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5bd67d88a8
This is the radio found in NXP Kinetis KW41Z, KW21Z. Only 802.15.4 mode is implemented (KW41Z also supports BLE on the same transceiver). The driver uses vendor supplied initialization code for the low level XCVR hardware, these files were imported from KSDK 2.2.0 (framework_5.3.5)
236 lines
8.7 KiB
C
236 lines
8.7 KiB
C
/*
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* Copyright (C) 2017 SKF AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup drivers_kw41zrf
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* @{
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* @file
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* @brief Internal function of kw41zrf driver
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @}
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*/
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#include "log.h"
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#include "irq.h"
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#include "panic.h"
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#include "kw41zrf.h"
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#include "kw41zrf_getset.h"
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#include "kw41zrf_intern.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/**
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* @brief Delay before entering deep sleep mode, in DSM_TIMER ticks (32.768 kHz)
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*
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* @attention must be >= 4 according to SoC ref. manual
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*/
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#define KW41ZRF_DSM_ENTER_DELAY 5
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/**
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* @brief Delay before leaving deep sleep mode, in DSM_TIMER ticks (32.768 kHz)
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*
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* @attention must be >= 4 according to SoC ref. manual
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*/
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#define KW41ZRF_DSM_EXIT_DELAY 5
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struct {
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void (*cb)(void *arg); /**< Callback function called from radio ISR */
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void *arg; /**< Argument to callback */
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} isr_config;
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void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg)
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{
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unsigned int mask = irq_disable();
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isr_config.cb = cb;
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isr_config.arg = arg;
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irq_restore(mask);
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}
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void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm)
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{
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DEBUG("[kw41zrf] set power mode to %u\n", pm);
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unsigned state = irq_disable();
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switch (pm) {
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case KW41ZRF_POWER_IDLE:
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{
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/* Disable some CPU power management if we need to be active, otherwise the
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* radio will be stuck in state retention mode. */
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if (!dev->pm_blocked) {
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PM_BLOCK(KW41ZRF_PM_BLOCKER);
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dev->pm_blocked = 1;
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}
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/* Restore saved RF oscillator settings, enable oscillator in RUN mode
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* to allow register access */
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/* This is also where the oscillator is enabled during kw41zrf_init:
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* kw41zrf_init -> kw41zrf_reset_phy -> kw41zrf_set_power_mode
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* => Do not return before this line during init */
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RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN(1);
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/* Assume DSM timer has been running since we entered sleep mode */
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/* In case it was not already running, however, we still set the
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* enable flag here. */
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/* RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN lets the link layer
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* request the RF oscillator to remain on during STOP and VLPS, to
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* allow stopping the CPU core without affecting TX or RX operations */
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RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK |
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RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK);
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/* Wait for oscillator ready signal before attempting to recover from DSM */
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while ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {}
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KW41ZRF_LED_NDSM_ON;
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/* If we are already awake we can just return now. */
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if (!(kw41zrf_is_dsm())) {
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/* Already awake */
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break;
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}
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/* The wake target must be at least (4 + RSIM_DSM_OSC_OFFSET) ticks
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* into the future, to let the oscillator stabilize before switching
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* on the clocks */
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RSIM->ZIG_WAKE = KW41ZRF_DSM_EXIT_DELAY + RSIM->DSM_TIMER + RSIM->DSM_OSC_OFFSET;
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/* Wait to come out of DSM */
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while (kw41zrf_is_dsm()) {}
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/* Convert DSM ticks (32.768 kHz) to event timer ticks (1 MHz) */
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uint64_t tmp = (uint64_t)(RSIM->ZIG_WAKE - RSIM->ZIG_SLEEP) * 15625ul;
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uint32_t usec = (tmp >> 9); /* equivalent to (usec / 512) */
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/* Add the offset */
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ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK |
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ZLL_EVENT_TMR_EVENT_TMR(usec);
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/* Clear IRQ flags */
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uint32_t irqsts = ZLL->IRQSTS;
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DEBUG("[kw41zrf] wake IRQSTS=%" PRIx32 "\n", irqsts);
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ZLL->IRQSTS = irqsts;
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/* Disable DSM timer triggered sleep */
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ZLL->DSM_CTRL = 0;
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break;
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}
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case KW41ZRF_POWER_DSM:
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{
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if (kw41zrf_is_dsm()) {
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/* Already asleep */
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break;
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}
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if (dev->pm_blocked) {
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PM_UNBLOCK(KW41ZRF_PM_BLOCKER);
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dev->pm_blocked = 0;
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}
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/* Race condition: if sleep is re-triggered after wake before the
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* DSM_ZIG_FINISHED flag has been switched off, then the RSIM
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* becomes stuck and never enters DSM.
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* The time from ZIG_WAKE until DSM_ZIG_FINISHED is turned off seem
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* to be constant at 2 DSM ticks */
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while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK) {}
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/* Clear IRQ flags */
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uint32_t irqsts = RSIM->DSM_CONTROL;
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RSIM->DSM_CONTROL = irqsts;
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irqsts = ZLL->IRQSTS;
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DEBUG("[kw41zrf] sleep IRQSTS=%" PRIx32 "\n", irqsts);
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ZLL->IRQSTS = irqsts;
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NVIC_ClearPendingIRQ(Radio_1_IRQn);
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/* Enable timer triggered sleep */
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ZLL->DSM_CTRL = ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK;
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/* The device will automatically wake up 8.5 minutes from now if not
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* awoken sooner by software */
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/* TODO handle automatic wake in the ISR if it becomes an issue */
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RSIM->ZIG_WAKE = RSIM->DSM_TIMER - KW41ZRF_DSM_EXIT_DELAY - RSIM->DSM_OSC_OFFSET;
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/* Set sleep start time */
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/* The target time must be at least 4 DSM_TIMER ticks into the future */
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RSIM->ZIG_SLEEP = RSIM->DSM_TIMER + KW41ZRF_DSM_ENTER_DELAY;
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/* Start the 32.768 kHz DSM timer in case it was not already running */
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/* If ZIG_SYSCLK_REQUEST_EN is not set then the hardware will not
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* enter DSM and we get stuck in the while() below */
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RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK |
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RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK);
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while (!(kw41zrf_is_dsm())) {}
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KW41ZRF_LED_NDSM_OFF;
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/* Restore saved RF_OSC_EN bits (from kw41zrf_init)
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* This will disable the RF oscillator unless the system was
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* configured to use the RF oscillator before kw41zrf_init() was
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* called, for example when using the RF oscillator for the CPU core
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* clock. */
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RSIM->CONTROL = (RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) |
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dev->rf_osc_en_idle;
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/* Let the DSM timer run until we exit deep sleep mode */
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break;
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}
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default:
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LOG_ERROR("[kw41zrf] Unknown power mode %u\n", pm);
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break;
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}
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irq_restore(state);
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}
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void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq)
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{
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(void) dev;
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DEBUG("[kw41zrf] set sequence to %x\n", (unsigned)seq);
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assert(!kw41zrf_is_dsm());
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unsigned back_to_sleep = 0;
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if (seq == XCVSEQ_DSM_IDLE) {
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back_to_sleep = 1;
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seq = XCVSEQ_IDLE;
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}
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else if ((seq == XCVSEQ_RECEIVE) && dev->recv_blocked) {
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/* Wait in standby until recv has been called to avoid corrupting the RX
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* buffer before the frame has been received by the higher layers */
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seq = XCVSEQ_IDLE;
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}
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uint32_t seq_old = ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK;
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if (seq_old != XCVSEQ_IDLE && seq_old != XCVSEQ_RECEIVE) {
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LOG_ERROR("[kw41zrf] seq not idle: 0x%" PRIu32 "\n", seq_old);
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assert(0);
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}
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kw41zrf_abort_sequence(dev);
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ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | ZLL_PHY_CTRL_SEQMSK_MASK)) | seq;
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while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >>
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ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != (ZLL_PHY_CTRL_XCVSEQ_MASK & seq)) {}
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if (back_to_sleep) {
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kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM);
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}
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}
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int kw41zrf_can_switch_to_idle(kw41zrf_t *dev)
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{
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(void) dev;
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if (!kw41zrf_is_dsm()) {
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uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT;
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DEBUG("[kw41zrf] XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 ", SEQ_CTRL_STS=0x%" PRIx32 "\n", seq,
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ZLL->SEQ_STATE, ZLL->SEQ_CTRL_STS);
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switch (seq)
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{
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case XCVSEQ_TRANSMIT:
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case XCVSEQ_TX_RX:
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case XCVSEQ_CCA:
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/* We should wait until TX or CCA has finished before moving to
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* another mode */
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return 0;
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default:
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break;
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}
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}
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return 1;
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}
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void isr_radio_1(void)
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{
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DEBUG("[kw41zrf] INT1\n");
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if (isr_config.cb != NULL) {
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isr_config.cb(isr_config.arg);
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}
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cortexm_isr_end();
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}
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