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8bab36f1c5
Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
32 lines
889 B
Plaintext
32 lines
889 B
Plaintext
# Copyright (c) 2020 Inria
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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config CPU_FAM_G0
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bool
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select CPU_STM32
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select CPU_CORE_CORTEX_M0PLUS
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select HAS_CPU_STM32G0
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_FLASHPAGE_RAW
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
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select HAS_PERIPH_VBAT
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select HAS_PERIPH_WDT
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select HAS_BOOTLOADER_STM32
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config CPU_FAM
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default "g0" if CPU_FAM_G0
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config HAS_CPU_STM32G0
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bool
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help
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Indicates that the cpu being used belongs to the 'stm32g0' family.
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