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https://github.com/RIOT-OS/RIOT.git
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183 lines
4.7 KiB
C
183 lines
4.7 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo-l031k6 STM32 Nucleo-L031K6
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* @ingroup boards_common_nucleo32
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* @brief Support for the STM32 Nucleo-L031K6
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-l031k6 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Aabdie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSI (16000000U) /* internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 15),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF4,
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.tx_af = GPIO_AF4,
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.bus = APB1,
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.irqn = USART2_IRQn
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}
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM21,
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.rcc_mask = RCC_APB2ENR_TIM21EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 6) /* D5 */, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF5,
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.bus = APB2
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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},
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{ /* for APB2 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_B, 5),
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.miso_pin = GPIO_PIN(PORT_B, 4),
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.sclk_pin = GPIO_PIN(PORT_B, 3),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF0,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_CONFIG { \
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{ GPIO_PIN(PORT_A, 0), 0 }, /* Pin A0 */ \
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{ GPIO_PIN(PORT_A, 1), 1 }, /* Pin A1 */ \
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{ GPIO_PIN(PORT_A, 3), 3 }, /* Pin A2 */ \
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{ GPIO_PIN(PORT_A, 4), 4 }, /* Pin A3 */ \
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{ GPIO_PIN(PORT_A, 5), 5 }, /* Pin A4 */ \
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{ GPIO_PIN(PORT_A, 6), 6 }, /* Pin A5 */ \
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{ GPIO_PIN(PORT_A, 7), 7 }, /* Pin A6 */ \
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}
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#define ADC_NUMOF (7U)
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/** @} */
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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