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69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
/*
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* Copyright 2016, Imagination Technologies Limited and/or its
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* affiliated group companies.
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_mips32r2_commom
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* @{
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*
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* @file
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* @brief API for supporting External Interrupt Controllers (EIC mode)
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*
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* @author Neil Jones <neil.jones@imgtec.com>
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*/
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#ifndef EIC_IRQ_H
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#define EIC_IRQ_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @ brief Internal Interrupt numbers
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*
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* MIPS cores have a few internally generated interrupts from the Timer,
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* Performance Counters and Fast Debug Channel hardware, in EIC mode these
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* become outputs from the core and are connected to the external controller,
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* the external control then loops these back at whichever IPL it decides
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*
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* We use negative numbers to represent these, leaving positive numbers free for
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* the SoC specific interrupts
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* @{
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*/
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#define EIC_IRQ_TIMER (-1)
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#define EIC_IRQ_FDC (-2)
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#define EIC_IRQ_PC (-3)
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/** @} */
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/**
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* @brief Configure and route the interrupt
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*/
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void eic_irq_configure(int irq_num);
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/**
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* @brief Enable an interrupt
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*/
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void eic_irq_enable(int irq_num);
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/**
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* @brief Disable an interrupt
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*/
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void eic_irq_disable(int irq_num);
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/**
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* @brief Acknowledge an interrupt
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*/
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void eic_irq_ack(int irq_num);
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#ifdef __cplusplus
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}
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#endif
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#endif /* EIC_IRQ_H */
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/** @} */
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