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336 lines
15 KiB
Plaintext
336 lines
15 KiB
Plaintext
/**
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* @defgroup cpu_kinetis NXP Kinetis
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* @ingroup cpu
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* @brief NXP Kinetis Cortex-M MCU specific implementation
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*/
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/**
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* @defgroup cpu_kinetis_adc Kinetis ADC
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* @ingroup cpu_kinetis
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* @brief Kinetis ADC driver
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*
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* ### ADC configuration example (for periph_conf.h) ###
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*
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* static const adc_conf_t adc_config[] = {
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* { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, // ADC0_DP0
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* { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, // ADC0_DM0
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* { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, // ADC1_DP0
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* { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, // ADC1_DM0
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* { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, // PTB0
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* { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, // PTB1
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* { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, // PTC1
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* { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, // PTC2
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* };
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* #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
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*/
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/**
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* @defgroup cpu_kinetis_cpuid Kinetis CPUID
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* @ingroup cpu_kinetis
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* @brief Kinetis CPUID driver
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*
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* No configuration is necessary.
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*/
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/**
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* @defgroup cpu_kinetis_gpio Kinetis GPIO
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* @ingroup cpu_kinetis
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* @brief Kinetis GPIO driver
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*
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* The GPIO driver uses the @ref GPIO_PIN(port, pin) macro to declare pins.
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*
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* No configuration is necessary.
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*/
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/**
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* @defgroup cpu_kinetis_i2c Kinetis I2C
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* @ingroup cpu_kinetis
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* @brief Kinetis I2C driver
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*
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* ### I2C configuration example (for periph_conf.h) ###
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*
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* #define I2C_NUMOF (1U)
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* #define I2C_0_EN 1
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*
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* / * Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 * /
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* #define KINETIS_I2C_F_ICR_LOW (0x3D)
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* #define KINETIS_I2C_F_MULT_LOW (2)
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* / * Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 * /
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* #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
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* #define KINETIS_I2C_F_MULT_NORMAL (1)
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* / * Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 * /
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* #define KINETIS_I2C_F_ICR_FAST (0x17)
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* #define KINETIS_I2C_F_MULT_FAST (0)
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* / * Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 * /
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* #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
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* #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
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*
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* // I2C 0 device configuration
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* #define I2C_0_DEV I2C1
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* #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
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* #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
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* #define I2C_0_IRQ I2C1_IRQn
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* #define I2C_0_IRQ_HANDLER isr_i2c1
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* // I2C 0 pin configuration
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* #define I2C_0_PORT PORTE
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* #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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* #define I2C_0_PIN_AF 6
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* #define I2C_0_SDA_PIN 0
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* #define I2C_0_SCL_PIN 1
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* #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
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*/
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/**
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* @defgroup cpu_kinetis_pwm Kinetis PWM
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* @ingroup cpu_kinetis
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* @brief Kinetis PWM driver
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*
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* ### PWM configuration example (for periph_conf.h) ###
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*
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* #define PWM_NUMOF (1U)
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* #define PWM_0_EN 1
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* #define PWM_MAX_CHANNELS 2
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*
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* // PWM 0 device configuration
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* #define PWM_0_DEV FTM0
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* #define PWM_0_CHANNELS 2
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* #define PWM_0_CLK (48e6)
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* #define PWM_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_FTM0_MASK))
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* #define PWM_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_FTM0_MASK))
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* // PWM 0 pin configuration
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* #define PWM_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTA_MASK))
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*
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* #define PWM_0_PIN_CH0 4
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* #define PWM_0_FTMCHAN_CH0 1
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* #define PWM_0_PORT_CH0 PORTA
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* #define PWM_0_PIN_AF_CH0 3
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*
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* #define PWM_0_PIN_CH1 4
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* #define PWM_0_FTMCHAN_CH1 4
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* #define PWM_0_PORT_CH1 PORTD
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* #define PWM_0_PIN_AF_CH1 4
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*/
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/**
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* @defgroup cpu_kinetis_rnga Kinetis RNGA
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* @ingroup cpu_kinetis
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* @brief Driver for NXP Kinetis RNGA module. RNGA generates data that
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* looks random. Reference Manual recommends to use the RNGA as entropy
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* source.
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*
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* ### RNGA configuration example (for periph_conf.h) ###
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*
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* #define RANDOM_NUMOF (1U)
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* #define KINETIS_RNGA RNG
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* #define RANDOM_CLKEN() (SIM->SCGC6 |= (1 << 9))
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* #define RANDOM_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
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*/
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/**
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* @defgroup cpu_kinetis_rngb Kinetis RNGB
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* @ingroup cpu_kinetis
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* @brief Low-level random number generator driver implementation.
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* Driver for NXP Kinetis RNGB module. RNGB generates data that
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* looks random. Reference Manual recommends to use the RNGB as entropy
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* source.
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*
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* ### RNGB configuration example (for periph_conf.h) ###
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*
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* #define RANDOM_NUMOF (1U)
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* #define KINETIS_RNGB RNG
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* #define RANDOM_CLKEN() (SIM->SCGC6 |= (1 << 9))
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* #define RANDOM_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
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*/
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/**
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* @defgroup cpu_kinetis_rtc Kinetis RTC
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* @ingroup cpu_kinetis
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* @brief Kinetis RTC driver
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*
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* RTC is clocked by a 32.768 kHz clock.
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*
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* Please note the manual of your MCU or SiP for the
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* clock setting for the RTC module. After initialization
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* Time Seconds Register (TSR) increments once a second.
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* The TSR (also TAR) value will be converted to the stuct tm
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* and back with the help of stdlib functions that are
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* defined in time.h.
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* The driver supports alarm, it is stored in the
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* Time Alarm Registers (TAR) and the unit is seconds.
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*
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* ### RTC configuration example (for periph_conf.h) ###
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*
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* #define RTC_NUMOF (1U)
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* #define RTC_DEV RTC
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* #define RTC_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
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*
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* Optional settings to configure internal load capacitors (see
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* reference manual):
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*
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* #define RTC_LOAD_CAP_BITS 0
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*/
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/**
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* @defgroup cpu_kinetis_spi Kinetis SPI
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* @ingroup cpu_kinetis
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* @brief Kinetis SPI driver
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*
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* The SPI baud rate and other timings are generated from the bus
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* clock via prescalers, the hardware module allows for very
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* detailed timing configuration, but a tool exists to generate a
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* standard timing configuration for any given module clock frequency.
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* The timing configuration tool is found in
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* cpu/kinetis/dist/calc_spi_scalers
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*
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* Finer tuning of timings than the RIOT SPI API is capable of is
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* supported by modifying the generated configuration. See the
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* reference manual for your Kinetis CPU (Chapter: "SPI module,
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* Functional description, Module baud rate and clock delay
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* generation") for a description of each delay.
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*
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* The SPI driver supports using GPIO pins for chip select, as an
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* alternative to using hardware chip select.
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* The pins specified in spi_config[x].pin_cs[y] are the hardware
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* chip select pins, designated SPIx_PCSy in the hardware reference
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* documentation. These pins can not be chosen arbitrarily but must
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* be selected from the pins which support the SPIx_PCSy function
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* in the pin multiplexing table found in the reference manual.
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*
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* To use a hardware controlled chip select pin, use the SPI_HWCS
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* macro instead of GPIO_PIN when calling spi_acquire() in the
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* device driver.
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* Software managed CS signals can use any GPIO pin, at the cost of
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* extra delays in the transfer because of the additional overhead
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* of calling gpio_set/clear at every transfer.
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*
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* ### SPI configuration example (for periph_conf.h): ###
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*
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* static const uint32_t spi_clk_config[] = {
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* // Use cpu/kinetis/dist/calc_spi_scalers to
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* // generate the timing configuration
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* };
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*
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* static const spi_conf_t spi_config[] = {
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* {
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* .dev = SPI0,
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* .pin_miso = GPIO_PIN(PORT_D, 3),
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* .pin_mosi = GPIO_PIN(PORT_D, 2),
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* .pin_clk = GPIO_PIN(PORT_D, 1),
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* .pin_cs = {
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* GPIO_PIN(PORT_D, 0),
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* GPIO_PIN(PORT_D, 4),
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* GPIO_PIN(PORT_D, 5),
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* GPIO_PIN(PORT_D, 6),
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* GPIO_UNDEF
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* },
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* .pcr = GPIO_AF_2,
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* .simmask = SIM_SCGC6_SPI0_MASK
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* },
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* {
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* .dev = SPI1,
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* .pin_miso = GPIO_PIN(PORT_E, 3),
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* .pin_mosi = GPIO_PIN(PORT_E, 1),
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* .pin_clk = GPIO_PIN(PORT_E, 2),
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* .pin_cs = {
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* GPIO_PIN(PORT_E, 4),
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* GPIO_UNDEF,
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* GPIO_UNDEF,
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* GPIO_UNDEF,
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* GPIO_UNDEF
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* },
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* .pcr = GPIO_AF_2,
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* .simmask = SIM_SCGC6_SPI1_MASK
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* }
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* };
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*
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* #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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*/
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/**
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* @defgroup cpu_kinetis_timer Kinetis Timer
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* @ingroup cpu_kinetis
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* @brief Periodic Interrupt Timer (PIT) and Low-Power Timer (LPTMR) driver.
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*
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* The PIT is a count down timer, in order to use it with riot-os
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* a count up timer will be simulated. The PIT has four channels,
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* each two channels are cascaded. The n-1 channel is a prescaler
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* and the n channel a down counter. In standard configuration
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* with four channels, two simulated count up timer are possible.
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*
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* To counteract the effects of the asynchronous operation of the
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* LPTMR, this driver uses the RTT as a time base which the LPTMR
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* is referenced against. This method reduces the timing jitter
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* caused by mixing the clock domains of the bus clock used by the
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* CPU and the 32kHz reference clock for the LPTMR counter.
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*
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* ### Timer configuration example (for periph_conf.h) ###
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*
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* #define PIT_NUMOF (2U)
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* #define PIT_CONFIG { \
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* { \
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* .prescaler_ch = 0, \
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* .count_ch = 1, \
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* }, \
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* { \
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* .prescaler_ch = 2, \
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* .count_ch = 3, \
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* }, \
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* }
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* #define LPTMR_NUMOF (1U)
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* #define LPTMR_CONFIG { \
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* { \
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* .dev = LPTMR0, \
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* .irqn = LPTMR0_IRQn, \
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* } \
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* }
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* #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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*
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* #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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* #define PIT_ISR_0 isr_pit1
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* #define PIT_ISR_1 isr_pit3
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* #define LPTMR_ISR_0 isr_lptmr0
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*/
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/**
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* @defgroup cpu_kinetis_uart Kinetis UART
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* @ingroup cpu_kinetis
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* @brief Kinetis UART driver
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*
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* There are different implementations of the UART interface.
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* The treatment of interrupts is also slightly different.
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* The register UARTx_BDH to UARTx_C4 look almost the same.
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* We distinguish the type of the UART
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* using the BRFA field in the UART C4 register.
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* Currently, only the base TX/RX functionality is available.
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*
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* ### UART configuration example (for periph_conf.h) ###
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*
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* static const uart_conf_t uart_config[] = {
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* {
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* .dev = UART0,
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* .freq = CLOCK_CORECLOCK,
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* .pin_rx = GPIO_PIN(PORT_A, 14),
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* .pin_tx = GPIO_PIN(PORT_A, 15),
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* .pcr_rx = PORT_PCR_MUX(3),
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* .pcr_tx = PORT_PCR_MUX(3),
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* .irqn = UART0_RX_TX_IRQn,
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* .scgc_addr = &SIM->SCGC4,
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* .scgc_bit = SIM_SCGC4_UART0_SHIFT,
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* .mode = UART_MODE_8N1,
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* },
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* {
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* .dev = UART1,
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* .freq = CLOCK_CORECLOCK,
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* .pin_rx = GPIO_PIN(PORT_C, 3),
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* .pin_tx = GPIO_PIN(PORT_C, 4),
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* .pcr_rx = PORT_PCR_MUX(3),
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* .pcr_tx = PORT_PCR_MUX(3),
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* .irqn = UART1_RX_TX_IRQn,
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* .scgc_addr = &SIM->SCGC4,
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* .scgc_bit = SIM_SCGC4_UART1_SHIFT,
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* .mode = UART_MODE_8N1,
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* },
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* };
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* #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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*/
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