Steffen Pengel 35635e4039 stm32f3: periph: uart: add misssing uart overrun handling ... On overrung the ORE bit in the ORECF register is set. An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The ORE bit is reset by setting the ORECF bit in the ICR register. In case the ORE bit isn't cleared, the isr_handler() routine is called continuously. Which prevents the system from normal scheduling.		2016-02-21 20:30:29 +01:00
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gpio.c	STM32 GPIO: Fix exti_isr handling to only call callbacks of lines with have there interrupt enabled	2016-02-21 09:43:42 +01:00
i2c.c	cpu: removed init_slave from I2C drivers	2015-10-20 16:57:39 +02:00
Makefile	cpu: Initial import of stm32f3	2014-07-31 19:38:26 +02:00
pwm.c	cpu/stm32f3: adapted to PWM interface changes	2016-02-12 16:09:58 +01:00
spi.c	cpu: stm32f3: spi: remove unused vtimer include	2015-11-10 12:26:58 +01:00
timer.c	cpu/stm32f3: Update to match timer_init API change	2016-02-13 21:29:36 +01:00
uart.c	stm32f3: periph: uart: add misssing uart overrun handling	2016-02-21 20:30:29 +01:00