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1a0da9a7af
clock.c: The MSP430 may need nop instructions after (and in some cases
even before) touching the global interrupt enable bit in the
status register. The assembler generates a warning when in
doubt. Those nops should not be needed in our cases, but maybe
it is better two waste flash for two instructions than having
to live with the warning.
cpu.c: drop unneeded include
136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
/*
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* Copyright (C) 2016 Kaspar Schleiser <kaspar@schleiser.de>
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* 2014, Freie Universitaet Berlin (FUB) & INRIA.
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* All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#include "cpu.h"
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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/*
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* This function can both be called from ISR and from thread context.
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*
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* In both cases, the caller will use "CALL", which pushes the return
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* address on the stack before executing the function's first instruction.
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*
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* If called within ISR, just set sched_context_switch_request and
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* directly return to the call site. A regular function return does this.
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*
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* If called from stack context, it needs to prepare the stack so it looks exactly
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* as if the thread had been interrupted by an ISR, which requires the SR to be on
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* stack right after the return address. So we do this manually.
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* __save_context() will then save the remaining registers, then store the stack
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* pointer in the thread's thread_t.
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*
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* At this point, the thread context is properly saved. sched_run (possibly) changes
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* the currently active thread, which __restore_context() then restores, resuming
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* execution at the call site using reti.
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*
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*/
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void thread_yield_higher(void)
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{
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if (irq_is_in()) {
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sched_context_switch_request = 1;
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}
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else {
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__asm__ volatile (
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"push r2" "\n\t" /* save SR */
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"dint" "\n\t" /* reti will restore SR, and thus, IRQ state */
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"nop" "\n\t" /* dint takes an additional CPU cycle to take into effect */
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: /* no outputs */
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: /* no inputs */
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: /* no clobbers */
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);
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__save_context();
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/* have thread_get_active() point to the next thread */
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sched_run();
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__restore_context();
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UNREACHABLE();
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}
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}
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/* This function calculates the ISR_usage */
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int thread_isr_stack_usage(void)
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{
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/* TODO */
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return -1;
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}
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void *thread_isr_stack_pointer(void)
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{
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/* TODO */
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return (void *)-1;
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}
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void *thread_isr_stack_start(void)
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{
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/* TODO */
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return (void *)-1;
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}
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NORETURN void cpu_switch_context_exit(void)
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{
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sched_run();
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__restore_context();
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UNREACHABLE();
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}
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/**
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* mspgcc handles main specially - it does not return but falls
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* through to section .fini9.
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* To "fix" this, we put a return in section .fini9 to make main
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* behave like a regular function. This enables a common
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* thread_stack_init behavior. */
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__attribute__((section (".fini9"))) void __main_epilogue(void) { __asm__("ret"); }
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/* ------------------------------------------------------------------------- */
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/* Processor specific routine - here for MSP */
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/* ------------------------------------------------------------------------- */
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char *thread_stack_init(thread_task_func_t task_func, void *arg, void *stack_start, int stack_size)
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{
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unsigned short stk = (unsigned short)((uintptr_t) stack_start + stack_size);
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/* ensure correct stack alignment (on 16-bit boundary) */
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stk &= 0xfffe;
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unsigned short *stackptr = (unsigned short *)stk;
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/* now make SP point on the first AVAILABLE slot in stack */
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--stackptr;
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*stackptr = (unsigned short) sched_task_exit;
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--stackptr;
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*stackptr = (unsigned short) task_func;
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--stackptr;
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/* initial value for SR */
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*stackptr = GIE;
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--stackptr;
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/* Space for registers. */
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for (unsigned int i = 15; i > 4; i--) {
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*stackptr = i;
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--stackptr;
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}
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/* set arg to R12
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this was R15 in mspgcc, see https://www.ti.com/lit/an/slaa664/slaa664.pdf
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stackptr points to R3, so write arg 9 words after that.
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*/
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stackptr[8] = (intptr_t)arg;
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return (char *) stackptr;
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}
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