Benjamin Valentin 736e5e5a35 cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK ... There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.		2019-09-27 10:49:43 +02:00
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periph_cpu.h	cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK	2019-09-27 10:49:43 +02:00