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111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of common STM32 clock configuration functions
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
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defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32WL)
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#define REG_PWR_CR CR1
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#define BIT_CR_DBP PWR_CR1_DBP
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#else
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#define REG_PWR_CR CR
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#define BIT_CR_DBP PWR_CR_DBP
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#endif
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#if defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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#define REG_LSE CSR
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#define BIT_LSEON RCC_CSR_LSEON
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#define BIT_LSERDY RCC_CSR_LSERDY
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#else
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#define REG_LSE BDCR
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#define BIT_LSEON RCC_BDCR_LSEON
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#define BIT_LSERDY RCC_BDCR_LSERDY
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#endif
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#if defined (CPU_FAM_STM32WB)
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#define RCC_CFGR_SWS_HSI RCC_CFGR_SWS_0
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#define RCC_CSR_LSION RCC_CSR_LSI1ON
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#define RCC_CSR_LSIRDY RCC_CSR_LSI1RDY
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#endif
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#if defined(CPU_FAM_STM32L5)
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#define RCC_CFGR_SWS_HSI RCC_CFGR_SWS_0
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#endif
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void stmclk_enable_hsi(void)
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{
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY)) {}
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}
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void stmclk_disable_hsi(void)
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{
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RCC->CR &= ~RCC_CR_HSION;
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}
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void stmclk_enable_lfclk(void)
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{
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if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
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stmclk_dbp_unlock();
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RCC->REG_LSE |= BIT_LSEON;
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while (!(RCC->REG_LSE & BIT_LSERDY)) {}
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/* Set LSE system clock enable bit. This is required if LSE is to be used by
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USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode */
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#if defined(CPU_FAM_STM32WL)
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RCC->BDCR |= RCC_BDCR_LSESYSEN;
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while (!(RCC->BDCR & RCC_BDCR_LSESYSRDY)) {}
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#endif
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stmclk_dbp_lock();
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}
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else {
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RCC->CSR |= RCC_CSR_LSION;
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
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}
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}
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void stmclk_disable_lfclk(void)
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{
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if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
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stmclk_dbp_unlock();
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RCC->REG_LSE &= ~(BIT_LSEON);
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while (!(RCC->REG_LSE & BIT_LSERDY)) {}
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stmclk_dbp_lock();
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}
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else {
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RCC->CSR &= ~(RCC_CSR_LSION);
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}
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}
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void stmclk_dbp_unlock(void)
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{
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PWR->REG_PWR_CR |= BIT_CR_DBP;
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}
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void stmclk_dbp_lock(void)
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{
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PWR->REG_PWR_CR &= ~(BIT_CR_DBP);
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}
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