mirror of
https://github.com/RIOT-OS/RIOT.git
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188 lines
4.1 KiB
C
188 lines
4.1 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_gd32v
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* @{
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*
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* @file
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* @brief GD32V GPIO implementation
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*
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* @author Koen Zandberg <koen@bergzand.net>
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*/
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#include "cpu.h"
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#include "clic.h"
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#include "periph_cpu.h"
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#include "periph/gpio.h"
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/**
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* @brief Extract information from mode parameter
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*/
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#define MODE_MASK (0x0f)
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#define ODR_POS (4U)
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/**
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* @brief Extract the port base address from the given pin identifier
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*/
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static inline GPIO_Type *_port(gpio_t pin)
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{
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return (GPIO_Type *)(pin & ~(0x0f));
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}
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/**
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* @brief Extract the port number form the given identifier
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*
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* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
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* register addresses.
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*/
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static inline int _port_num(gpio_t pin)
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{
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return (((pin >> 10) & 0x0f) - 2);
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}
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/**
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* @brief Extract the pin number from the last 4 bit of the pin identifier
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*/
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static inline int _pin_num(gpio_t pin)
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{
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return (pin & 0x0f);
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}
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static inline void _port_enable_clock(gpio_t pin)
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{
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periph_clk_en(APB2, (RCU_APB2EN_PAEN_Msk << _port_num(pin)));
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}
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/**
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* @brief Check if the given mode is some kind of input mode
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* @param[in] mode Mode to check
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* @retval 1 @p mode is GPIO_IN, GPIO_IN_PD, or GPIO_IN_PU
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* @retval 0 @p mode is not an input mode
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*/
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static inline int gpio_mode_is_input(gpio_mode_t mode)
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{
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return !(mode & 3);
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}
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static inline void _set_mode_or_af(GPIO_Type *port, unsigned pin_num,
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unsigned mode_or_af)
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{
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volatile uint32_t *crl = (&port->CTL0 + (pin_num >> 3));
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uint32_t tmp = *crl;
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tmp &= ~(0xf << ((pin_num & 0x7) * 4));
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tmp |= ((mode_or_af & MODE_MASK) << ((pin_num & 0x7) * 4));
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*crl = tmp;
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}
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static inline bool _pin_is_output(GPIO_Type *port, unsigned pin_num)
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{
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uint32_t reg = *(uint32_t *)(&port->CTL0 + (pin_num >> 3));
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return reg & (0x3 << ((pin_num & 0x7) << 2));
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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GPIO_Type *port = _port(pin);
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unsigned pin_num = _pin_num(pin);
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/* open-drain output with pull-up is not supported */
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if (mode == GPIO_OD_PU) {
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return -1;
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}
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/* enable the clock for the selected port */
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_port_enable_clock(pin);
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/* set pin mode */
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_set_mode_or_af(port, pin_num, mode);
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/* For input modes, ODR controls pull up settings */
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if (gpio_mode_is_input(mode)) {
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if (mode == GPIO_IN_PU) {
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cpu_reg_enable_bits(&port->OCTL, 1 << pin_num);
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}
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else {
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cpu_reg_disable_bits(&port->OCTL, 1 << pin_num);
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}
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}
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return 0; /* all OK */
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}
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void gpio_init_af(gpio_t pin, gpio_af_t af)
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{
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GPIO_Type *port = _port(pin);
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unsigned pin_num = _pin_num(pin);
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/* enable the clock for the selected port */
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_port_enable_clock(pin);
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/* configure the pin */
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_set_mode_or_af(port, pin_num, af);
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}
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void gpio_init_analog(gpio_t pin)
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{
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/* enable the GPIO port RCC */
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_port_enable_clock(pin);
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/* map the pin as analog input */
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int pin_num = _pin_num(pin);
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volatile uint32_t *pin_reg = (uint32_t *)(&_port(pin)->CTL0 + (pin_num >= 8));
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*pin_reg &= ~(0xfl << (4 * (pin_num - ((pin_num >= 8) * 8))));
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}
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int gpio_read(gpio_t pin)
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{
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GPIO_Type *port = _port(pin);
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unsigned pin_num = _pin_num(pin);
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if (_pin_is_output(port, pin)) {
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/* pin is output */
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return (port->OCTL & (1 << pin_num));
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}
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else {
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/* or input */
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return (port->ISTAT & (1 << pin_num));
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}
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}
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void gpio_set(gpio_t pin)
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{
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_port(pin)->BOP = (1 << _pin_num(pin));
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}
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void gpio_clear(gpio_t pin)
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{
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_port(pin)->BC = (1 << _pin_num(pin));
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}
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void gpio_toggle(gpio_t pin)
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{
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if (gpio_read(pin)) {
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gpio_clear(pin);
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}
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else {
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gpio_set(pin);
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}
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value) {
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gpio_set(pin);
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}
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else {
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gpio_clear(pin);
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}
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}
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/** @} */
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