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https://github.com/RIOT-OS/RIOT.git
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f375b00ff3
This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @brief Implementation specific CPU configuration options
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#if defined(CPU_SAML1X)
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#include "vendor/sam23.h"
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#elif defined(CPU_SAMD5X)
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#include "vendor/samd5x.h"
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#else
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#include "vendor/sam0.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
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#define CPU_FLASH_BASE FLASH_ADDR
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#ifdef CPU_SAML1X
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#define CPU_FLASH_RWWEE_BASE DATAFLASH_ADDR
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#else
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#define CPU_FLASH_RWWEE_BASE NVMCTRL_RWW_EEPROM_ADDR
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#endif
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/** @} */
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/**
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* @brief Flash page configuration
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* @{
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*/
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/* a flashpage in RIOT is mapped to a flash row on the SAM0s */
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#if defined(NVMCTRL_ROW_SIZE)
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#define FLASHPAGE_SIZE (NVMCTRL_ROW_SIZE)
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#elif defined(NVMCTRL_BLOCK_SIZE)
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#define FLASHPAGE_SIZE (NVMCTRL_BLOCK_SIZE)
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#elif defined(NVMCTRL_PAGE_SIZE)
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/* saml1x: The NVM is organized into rows, where each row contains four pages,
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as shown in the NVM Row Organization figure. */
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#define FLASHPAGE_SIZE (4 * NVMCTRL_PAGE_SIZE)
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#else
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#error "Unsupported Device"
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#endif
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/* one SAM0 row contains 4 SAM0 pages, so 4 SAM0 pages contain
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* the amount of a RIOT flashpage
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*/
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#define FLASHPAGE_PAGES_PER_ROW (FLASHPAGE_SIZE/FLASH_PAGE_SIZE)
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/* number of RIOT flashpages on device */
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#define FLASHPAGE_NUMOF (FLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
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/* The minimum block size which can be written is 16B. However, the erase
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* block is always FLASHPAGE_SIZE (SAM0 row).
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*/
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#define FLASHPAGE_RAW_BLOCKSIZE (16)
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/* Writing should be always 4 byte aligned */
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#define FLASHPAGE_RAW_ALIGNMENT (4)
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/* Add RWWEE memory if supported by revision of the chip
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* On some chips it is called RWW EEPROM while on some DATAFLASH, try to
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* catch all without relying on the CPU model but on the named defines
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*/
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#ifdef NVMCTRL_RWW_EEPROM_SIZE
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#define FLASHPAGE_RWWEE_NUMOF (NVMCTRL_RWWEE_PAGES / FLASHPAGE_PAGES_PER_ROW)
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#endif
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#ifdef DATAFLASH_SIZE
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#define FLASHPAGE_RWWEE_NUMOF (DATAFLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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