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https://github.com/RIOT-OS/RIOT.git
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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
215 lines
4.6 KiB
C
215 lines
4.6 KiB
C
/*
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* Copyright 2017 Ken Rabold
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_fe310
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* @{
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*
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* @file gpio.c
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* @brief Low-level GPIO implementation
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*
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* @author Ken Rabold
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* @}
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*/
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#include <stdlib.h>
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#include <unistd.h>
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#include "irq.h"
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#include "cpu.h"
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#include "periph_cpu.h"
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#include "periph_conf.h"
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#include "periph/gpio.h"
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#include "vendor/encoding.h"
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#include "vendor/platform.h"
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#include "vendor/plic_driver.h"
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/* Num of GPIOs supported */
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#define GPIO_NUMOF (32)
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static gpio_flank_t isr_flank[GPIO_NUMOF];
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static gpio_isr_ctx_t isr_ctx[GPIO_NUMOF];
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void gpio_isr(int num)
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{
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uint32_t pin = num - INT_GPIO_BASE;
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/* Invoke callback function */
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if (isr_ctx[pin].cb) {
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isr_ctx[pin].cb(isr_ctx[pin].arg);
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}
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/* Clear interupt */
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switch (isr_flank[pin]) {
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case GPIO_FALLING:
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GPIO_REG(GPIO_FALL_IP) |= (1 << pin);
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break;
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case GPIO_RISING:
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GPIO_REG(GPIO_RISE_IP) |= (1 << pin);
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break;
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case GPIO_BOTH:
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GPIO_REG(GPIO_FALL_IP) |= (1 << pin);
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GPIO_REG(GPIO_RISE_IP) |= (1 << pin);
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break;
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}
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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/* Check for valid pin */
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if (pin >= GPIO_NUMOF) {
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return -1;
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}
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/* Configure the mode */
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switch (mode) {
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case GPIO_IN:
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GPIO_REG(GPIO_INPUT_EN) |= (1 << pin);
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GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << pin);
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GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << pin);
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break;
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case GPIO_IN_PU:
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GPIO_REG(GPIO_INPUT_EN) |= (1 << pin);
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GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << pin);
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GPIO_REG(GPIO_PULLUP_EN) |= (1 << pin);
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break;
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case GPIO_OUT:
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GPIO_REG(GPIO_INPUT_EN) &= ~(1 << pin);
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GPIO_REG(GPIO_OUTPUT_EN) |= (1 << pin);
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GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << pin);
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break;
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default:
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return -1;
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}
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/* Configure the pin muxing for the GPIO */
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GPIO_REG(GPIO_IOF_EN) &= ~(1 << pin);
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GPIO_REG(GPIO_IOF_SEL) &= ~(1 << pin);
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return 0;
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}
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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/* Configure pin */
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if (gpio_init(pin, mode) != 0) {
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return -1;
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}
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/* Disable ext interrupts when setting up */
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clear_csr(mie, MIP_MEIP);
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/* Configure GPIO ISR with PLIC */
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set_external_isr_cb(INT_GPIO_BASE + pin, gpio_isr);
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PLIC_enable_interrupt(INT_GPIO_BASE + pin);
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PLIC_set_priority(INT_GPIO_BASE + pin, GPIO_INTR_PRIORITY);
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/* Configure the active flank(s) */
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gpio_irq_enable(pin);
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/* Save callback */
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isr_ctx[pin].cb = cb;
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isr_ctx[pin].arg = arg;
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isr_flank[pin] = flank;
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/* Re-eanble ext interrupts */
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set_csr(mie, MIP_MEIP);
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return 0;
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}
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void gpio_irq_enable(gpio_t pin)
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{
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/* Check for valid pin */
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if (pin >= GPIO_NUMOF) {
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return;
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}
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/* Enable interupt for pin */
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switch (isr_flank[pin]) {
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case GPIO_FALLING:
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GPIO_REG(GPIO_FALL_IE) |= (1 << pin);
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break;
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case GPIO_RISING:
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GPIO_REG(GPIO_RISE_IE) |= (1 << pin);
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break;
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case GPIO_BOTH:
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GPIO_REG(GPIO_FALL_IE) |= (1 << pin);
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GPIO_REG(GPIO_RISE_IE) |= (1 << pin);
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break;
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default:
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break;
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}
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}
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void gpio_irq_disable(gpio_t pin)
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{
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/* Check for valid pin */
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if (pin >= GPIO_NUMOF) {
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return;
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}
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/* Disable interupt for pin */
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switch (isr_flank[pin]) {
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case GPIO_FALLING:
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GPIO_REG(GPIO_FALL_IE) &= ~(1 << pin);
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break;
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case GPIO_RISING:
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GPIO_REG(GPIO_RISE_IE) &= ~(1 << pin);
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break;
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case GPIO_BOTH:
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GPIO_REG(GPIO_FALL_IE) &= ~(1 << pin);
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GPIO_REG(GPIO_RISE_IE) &= ~(1 << pin);
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break;
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default:
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break;
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}
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}
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int gpio_read(gpio_t pin)
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{
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return (GPIO_REG(GPIO_INPUT_VAL) & (1 << pin)) ? 1 : 0;
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}
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void gpio_set(gpio_t pin)
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{
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GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << pin);
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}
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void gpio_clear(gpio_t pin)
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{
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GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << pin);
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}
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void gpio_toggle(gpio_t pin)
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{
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GPIO_REG(GPIO_OUTPUT_VAL) ^= (1 << pin);
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value) {
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GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << pin);
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}
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else {
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GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << pin);
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}
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}
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