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eddd3177a5
AAPCS requires stack pointers to be aligned on a double word boundary. In addition, Clang-3.6 assumes the stack pointer is always aligned to a 8 byte boundary upon function entry, at least in armv7-m, causing hard-to-find errors in the compiled code.
257 lines
8.3 KiB
C
257 lines
8.3 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cortexm4_common
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* @{
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*
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* @file
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* @brief Implementation of the kernel's architecture dependent thread interface
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include <stdio.h>
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#include "arch/thread_arch.h"
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#include "sched.h"
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#include "thread.h"
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#include "irq.h"
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#include "cpu.h"
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#include "kernel_internal.h"
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/**
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* @name noticeable marker marking the beginning of a stack segment
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*
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* This marker is used e.g. by *thread_arch_start_threading* to identify the stacks start.
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*/
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#define STACK_MARKER (0x77777777)
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/**
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* @name ARM Cortex-M specific exception return value, that triggers the return to the task mode
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* stack pointer
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*/
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#define EXCEPT_RET_TASK_MODE (0xfffffffd)
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/**
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* Cortex-M knows stacks and handles register backups, so use different stack frame layout
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*
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* \todo Cortex-M thread_arch_stack_init: How to handle different Cortex-Ms? Code is so far valid for M3 and M4 without FPU
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*
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* Layout with storage of floating point registers (applicable for Cortex-M4):
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* ------------------------------------------------------------------------------------------------------------------------------------
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* | R0 | R1 | R2 | R3 | LR | PC | xPSR | S0 | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | S9 | S10 | S11 | S12 | S13 | S14 | S15 | FPSCR |
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* ------------------------------------------------------------------------------------------------------------------------------------
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*
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* Layout without floating point registers:
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* --------------------------------------
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* | R0 | R1 | R2 | R3 | LR | PC | xPSR |
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* --------------------------------------
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*
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*/
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char *thread_arch_stack_init(thread_task_func_t task_func,
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void *arg,
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void *stack_start,
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int stack_size)
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{
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uint32_t *stk;
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stk = (uint32_t *)((uintptr_t)stack_start + stack_size);
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/* adjust to 32 bit boundary by clearing the last two bits in the address */
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stk = (uint32_t *)(((uint32_t)stk) & ~((uint32_t)0x3));
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/* Stack start marker */
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stk--;
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*stk = STACK_MARKER;
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/* Make sure the stack is double word aligned (8 bytes) */
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/* This is required in order to conform with Procedure Call Standard for the
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* ARM® Architecture (AAPCS) */
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/* http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042e/IHI0042E_aapcs.pdf */
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if (((uint32_t) stk % 8) != 0) {
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/* add a single word padding */
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--stk;
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*stk = ~((uint32_t)STACK_MARKER);
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}
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/* TODO: fix FPU handling for Cortex-M4 */
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/*
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stk--;
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*stk = (unsigned int) 0;
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*/
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/* S0 - S15 */
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/*
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for (int i = 15; i >= 0; i--) {
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stk--;
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*stk = i;
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}
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*/
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/* ****************************** */
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/* Automatically popped registers */
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/* ****************************** */
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/* The following eight stacked registers are popped by the hardware upon
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* return from exception. (bx instruction in context_restore) */
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/* xPSR */
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stk--;
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/* Setting bit 9 (0x200) of xPSR will cause the initial stack pointer for
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* the process to be aligned on a 32-bit, non-64-bit, boundary. Don't do that. */
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/* Default xPSR, only the Thumb mode-bit is set */
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*stk = 0x01000000;
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/* pc */
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stk--;
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/* initial program counter */
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*stk = (uint32_t) task_func;
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/* lr */
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stk--;
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/* link register, return address when a thread exits. */
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*stk = (uint32_t) sched_task_exit;
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/* r12 */
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stk--;
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*stk = 0;
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/* r1 - r3 */
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for (int i = 3; i >= 1; i--) {
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stk--;
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*stk = i;
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}
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/* r0 */
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stk--;
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/* thread function parameter */
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*stk = (uint32_t) arg;
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/* 8 hardware-handled registers in total */
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/* ************************* */
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/* Manually popped registers */
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/* ************************* */
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/* The following registers are not handled by hardware in return from
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* exception, but manually by context_restore. */
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/* r11 - r4 */
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for (int i = 11; i >= 4; i--) {
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stk--;
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*stk = i;
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}
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/* exception return code */
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stk--;
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*stk = EXCEPT_RET_TASK_MODE; /* return to task-mode process stack pointer */
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/* 9 manually handled registers in total. */
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/* The returned stack pointer will be aligned on a 32 bit boundary not on a
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* 64 bit boundary because of the odd number of registers above (8+9).
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* This is not a problem since the initial stack pointer upon process entry
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* _will_ be 64 bit aligned (because of the cleared bit 9 in the stacked
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* xPSR and aligned stacking of the hardware-handled registers). */
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return (char*) stk;
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}
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void thread_arch_stack_print(void)
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{
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int count = 0;
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uint32_t *sp = (uint32_t *)sched_active_thread->sp;
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printf("printing the current stack of thread %" PRIkernel_pid "\n", thread_getpid());
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printf(" address: data:\n");
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do {
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printf(" 0x%08x: 0x%08x\n", (unsigned int)sp, (unsigned int)*sp);
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sp++;
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count++;
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} while (*sp != STACK_MARKER);
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printf("current stack size: %i byte\n", count);
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}
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__attribute__((naked)) void NORETURN thread_arch_start_threading(void)
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{
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/* enable IRQs to make sure the SVC interrupt is reachable */
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__ASM volatile ("bl irq_arch_enable\n");
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/* trigger the SVC interrupt which will get and execute the next thread */
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__ASM volatile ("svc #1\n");
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/* This line is unreachable, infinite loop */
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__ASM volatile (
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"unreachable%=:\n"
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"b unreachable%=\n"
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:::);
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}
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void thread_arch_yield(void)
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{
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/* trigger the PENDSV interrupt to run scheduler and schedule new thread if applicable */
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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}
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/**
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* @brief The svc is used for running the scheduler and scheduling a new task during start-up or
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* after a thread has exited
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*/
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void isr_svc(void);
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/**
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* @brief All task switching activity is carried out in the PendSV interrupt
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*/
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void isr_pendsv(void);
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__attribute__((naked)) void arch_context_switch(void)
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{
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/* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */
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__ASM volatile (
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/* PendSV handler entry point */
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".global isr_pendsv \n"
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".thumb_func \n"
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"isr_pendsv: \n"
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/* Save the context */
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/* save unsaved registers */
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".thumb_func \n"
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"context_save:"
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"mrs r0, psp \n" /* get stack pointer from user mode */
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"stmdb r0!,{r4-r11} \n" /* save regs */
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"stmdb r0!,{lr} \n" /* exception return value */
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/* "vstmdb sp!, {s16-s31} \n" */ /* TODO save FPU registers if needed */
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"ldr r1, =sched_active_thread \n" /* load address of current tcb */
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"ldr r1, [r1] \n" /* dereference pdc */
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"str r0, [r1] \n" /* write r0 to pdc->sp means current threads stack pointer */
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/* SVC handler entry point */
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/* PendSV will continue from above and through this part as well */
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".global isr_svc \n"
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".thumb_func \n"
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"isr_svc: \n"
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/* perform scheduling */
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"bl sched_run \n"
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/* Restore context and return from exception */
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".thumb_func \n"
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"context_restore: \n"
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"ldr r0, =sched_active_thread \n" /* load address of current TCB */
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"ldr r0, [r0] \n" /* dereference TCB */
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"ldr r1, [r0] \n" /* load tcb->sp to register 1 */
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"ldmia r1!, {r0} \n" /* restore exception return value from stack */
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/* "pop {s16-s31} \n" */ /* TODO load FPU register if needed depends on r0 exret */
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"ldmia r1!, {r4-r11} \n" /* restore other registers */
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"msr psp, r1 \n" /* restore PSP register (user mode SP)*/
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"bx r0 \n" /* load exception return value to PC causes end of exception*/
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/* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */
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);
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}
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