mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
Koen Zandberg
32399901f0
Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later
31 lines
694 B
Plaintext
31 lines
694 B
Plaintext
/*
|
|
* Copyright (C) 2017, 2019 Ken Rabold
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU Lesser
|
|
* General Public License v2.1. See the file LICENSE in the top level
|
|
* directory for more details.
|
|
*/
|
|
|
|
/**
|
|
* @addtogroup cpu_fe310
|
|
* @{
|
|
*
|
|
* @file
|
|
* @brief Memory definitions for the SiFive FE310
|
|
*
|
|
* @author Ken Rabold
|
|
* @author Koen Zandberg <koen@bergzand.net>
|
|
*
|
|
* @}
|
|
*/
|
|
INCLUDE fe310_vars.ld
|
|
|
|
MEMORY
|
|
{
|
|
flash (rxai!w) : ORIGIN = _rom_start_addr , LENGTH = _rom_length
|
|
ram (wxa!ri) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
|
|
itim (wxa!ri) : ORIGIN = _itim_start_addr, LENGTH = _itim_length
|
|
}
|
|
|
|
INCLUDE fe310_base.ld
|